Static linking in psram. Is there support or what is needed for it?

[Volkalex28]

Hello. Are there any plans to add a linking attribute to psram?
As in idf:
#[link_section = ".ext_ram.bss.****"]

[bjoernQ]

There are currently no plans to use PSRAM for anything but heap memory. PRs are welcome

[Volkalex28]

Why was it removed here?

[bjoernQ]

Why was it removed here?

It was never really supported ... e.g. we never actually zeroed .external.bss

[Volkalex28]

Added a draft for this. I will be glad for any help

[ProfFan]

I had some discussion with my coworkers today and realized that there is a huge benefit to this (PSRAM XIP): The PSRAM has much lower latency than the flash, so ICACHE misses will be much faster! XREF #1096 for example. Also per official docs: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/kconfig.html#config-spiram-fetch-instructions

Tagging @MabezDev since I saw the comments in #1090

[igrr]

The PSRAM has much lower latency than the flash, so ICACHE misses will be much faster!

@ProfFan I am curious about this conclusion, could you please explain it further? AFAICT, provided that Flash and PSRAM use same SPI bus width and frequency, read latencies would be the same (plus-minus a couple of dummy cycles after the address phase).

[ProfFan]

@igrr

I am curious about this conclusion

It's written in the official docs: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/kconfig.html#config-spiram-fetch-instructions

Also quote from docs:

The benefits of XiP from PSRAM is:

PSRAM access speed is faster than Flash access. So the performance is better.
The cache will not be disabled during an SPI1 flash operation, thus optimizing the code execution performance during SPI1 flash operations. For ISRs, ISR callbacks and data which might be accessed during this period, you do not need to place them in internal RAM, thus internal RAM usage can be optimized. This feature is useful for high throughput peripheral involved applications to improve the performance during SPI1 flash operations.