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Remove Deref to pac register block from peripheral singletons
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@bugadani
bugadani committed Jan 20, 2025
1 parent d1ee2ba commit 55db8da
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Showing 37 changed files with 1,261 additions and 1,306 deletions.
20 changes: 10 additions & 10 deletions esp-hal/src/aes/esp32.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,22 +13,22 @@ impl Aes<'_> {
}

pub(super) fn write_key(&mut self, key: &[u8]) {
let key_len = self.aes.key_iter().count();
let key_len = self.regs().key_iter().count();
debug_assert!(key.len() <= key_len * ALIGN_SIZE);
debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
self.alignment_helper
.volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len);
.volatile_write_regset(self.regs().key(0).as_ptr(), key, key_len);
}

pub(super) fn write_block(&mut self, block: &[u8]) {
let text_len = self.aes.text_iter().count();
let text_len = self.regs().text_iter().count();
debug_assert_eq!(block.len(), text_len * ALIGN_SIZE);
self.alignment_helper
.volatile_write_regset(self.aes.text(0).as_ptr(), block, text_len);
.volatile_write_regset(self.regs().text(0).as_ptr(), block, text_len);
}

pub(super) fn write_mode(&self, mode: Mode) {
self.aes.mode().write(|w| unsafe { w.bits(mode as _) });
self.regs().mode().write(|w| unsafe { w.bits(mode as _) });
}

/// Configures how the state matrix would be laid out
Expand All @@ -48,22 +48,22 @@ impl Aes<'_> {
to_write |= (input_text_word_endianess as u32) << 3;
to_write |= (output_text_byte_endianess as u32) << 4;
to_write |= (output_text_word_endianess as u32) << 5;
self.aes.endian().write(|w| unsafe { w.bits(to_write) });
self.regs().endian().write(|w| unsafe { w.bits(to_write) });
}

pub(super) fn write_start(&self) {
self.aes.start().write(|w| w.start().set_bit());
self.regs().start().write(|w| w.start().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
self.aes.idle().read().idle().bit_is_set()
self.regs().idle().read().idle().bit_is_set()
}

pub(super) fn read_block(&self, block: &mut [u8]) {
let text_len = self.aes.text_iter().count();
let text_len = self.regs().text_iter().count();
debug_assert_eq!(block.len(), text_len * ALIGN_SIZE);
self.alignment_helper
.volatile_read_regset(self.aes.text(0).as_ptr(), block, text_len);
.volatile_read_regset(self.regs().text(0).as_ptr(), block, text_len);
}
}

Expand Down
19 changes: 9 additions & 10 deletions esp-hal/src/aes/esp32cX.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,41 +6,40 @@ impl Aes<'_> {
}

fn write_dma(&mut self, enable_dma: bool) {
match enable_dma {
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
};
self.regs()
.dma_enable()
.write(|w| w.dma_enable().bit(enable_dma));
}

pub(super) fn write_key(&mut self, key: &[u8]) {
debug_assert!(key.len() <= 8 * ALIGN_SIZE);
debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
self.alignment_helper
.volatile_write_regset(self.aes.key(0).as_ptr(), key, 8);
.volatile_write_regset(self.regs().key(0).as_ptr(), key, 8);
}

pub(super) fn write_block(&mut self, block: &[u8]) {
debug_assert_eq!(block.len(), 4 * ALIGN_SIZE);
self.alignment_helper
.volatile_write_regset(self.aes.text_in(0).as_ptr(), block, 4);
.volatile_write_regset(self.regs().text_in(0).as_ptr(), block, 4);
}

pub(super) fn write_mode(&self, mode: Mode) {
self.aes.mode().write(|w| unsafe { w.bits(mode as _) });
self.regs().mode().write(|w| unsafe { w.bits(mode as _) });
}

pub(super) fn write_start(&self) {
self.aes.trigger().write(|w| w.trigger().set_bit());
self.regs().trigger().write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
self.aes.state().read().state().bits() == 0
self.regs().state().read().state().bits() == 0
}

pub(super) fn read_block(&self, block: &mut [u8]) {
debug_assert_eq!(block.len(), 4 * ALIGN_SIZE);
self.alignment_helper
.volatile_read_regset(self.aes.text_out(0).as_ptr(), block, 4);
.volatile_read_regset(self.regs().text_out(0).as_ptr(), block, 4);
}
}

Expand Down
22 changes: 11 additions & 11 deletions esp-hal/src/aes/esp32s2.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,31 +14,31 @@ impl Aes<'_> {
}

fn write_dma(&mut self, enable_dma: bool) {
self.aes
self.regs()
.dma_enable()
.write(|w| w.dma_enable().bit(enable_dma));
}

pub(super) fn write_key(&mut self, key: &[u8]) {
let key_len = self.aes.key_iter().count();
let key_len = self.regs().key_iter().count();
debug_assert!(key.len() <= key_len * ALIGN_SIZE);
debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
self.alignment_helper
.volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len);
.volatile_write_regset(self.regs().key(0).as_ptr(), key, key_len);
}

pub(super) fn write_block(&mut self, block: &[u8]) {
let text_in_len = self.aes.text_in_iter().count();
let text_in_len = self.regs().text_in_iter().count();
debug_assert_eq!(block.len(), text_in_len * ALIGN_SIZE);
self.alignment_helper.volatile_write_regset(
self.aes.text_in(0).as_ptr(),
self.regs().text_in(0).as_ptr(),
block,
text_in_len,
);
}

pub(super) fn write_mode(&self, mode: Mode) {
self.aes.mode().write(|w| unsafe { w.bits(mode as _) });
self.regs().mode().write(|w| unsafe { w.bits(mode as _) });
}

/// Configures how the state matrix would be laid out.
Expand All @@ -58,22 +58,22 @@ impl Aes<'_> {
to_write |= (input_text_word_endianess as u32) << 3;
to_write |= (output_text_byte_endianess as u32) << 4;
to_write |= (output_text_word_endianess as u32) << 5;
self.aes.endian().write(|w| unsafe { w.bits(to_write) });
self.regs().endian().write(|w| unsafe { w.bits(to_write) });
}

pub(super) fn write_start(&self) {
self.aes.trigger().write(|w| w.trigger().set_bit());
self.regs().trigger().write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
self.aes.state().read().state().bits() == 0
self.regs().state().read().state().bits() == 0
}

pub(super) fn read_block(&self, block: &mut [u8]) {
let text_out_len = self.aes.text_out_iter().count();
let text_out_len = self.regs().text_out_iter().count();
debug_assert_eq!(block.len(), text_out_len * ALIGN_SIZE);
self.alignment_helper.volatile_read_regset(
self.aes.text_out(0).as_ptr(),
self.regs().text_out(0).as_ptr(),
block,
text_out_len,
);
Expand Down
20 changes: 10 additions & 10 deletions esp-hal/src/aes/esp32s3.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,46 +6,46 @@ impl Aes<'_> {
}

fn write_dma(&mut self, enable_dma: bool) {
self.aes
self.regs()
.dma_enable()
.write(|w| w.dma_enable().bit(enable_dma));
}

pub(super) fn write_key(&mut self, key: &[u8]) {
let key_len = self.aes.key_iter().count();
let key_len = self.regs().key_iter().count();
debug_assert!(key.len() <= key_len * ALIGN_SIZE);
debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
self.alignment_helper
.volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len);
.volatile_write_regset(self.regs().key(0).as_ptr(), key, key_len);
}

pub(super) fn write_block(&mut self, block: &[u8]) {
let text_in_len = self.aes.text_in_iter().count();
let text_in_len = self.regs().text_in_iter().count();
debug_assert_eq!(block.len(), text_in_len * ALIGN_SIZE);
self.alignment_helper.volatile_write_regset(
self.aes.text_in(0).as_ptr(),
self.regs().text_in(0).as_ptr(),
block,
text_in_len,
);
}

pub(super) fn write_mode(&self, mode: Mode) {
self.aes.mode().write(|w| unsafe { w.bits(mode as _) });
self.regs().mode().write(|w| unsafe { w.bits(mode as _) });
}

pub(super) fn write_start(&self) {
self.aes.trigger().write(|w| w.trigger().set_bit());
self.regs().trigger().write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
self.aes.state().read().state().bits() == 0
self.regs().state().read().state().bits() == 0
}

pub(super) fn read_block(&self, block: &mut [u8]) {
let text_out_len = self.aes.text_out_iter().count();
let text_out_len = self.regs().text_out_iter().count();
debug_assert_eq!(block.len(), text_out_len * ALIGN_SIZE);
self.alignment_helper.volatile_read_regset(
self.aes.text_out(0).as_ptr(),
self.regs().text_out(0).as_ptr(),
block,
text_out_len,
);
Expand Down
23 changes: 14 additions & 9 deletions esp-hal/src/aes/mod.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,7 @@
//! * AES-DMA Initialization Vector (IV) is currently not supported
use crate::{
pac,
peripheral::{Peripheral, PeripheralRef},
peripherals::AES,
reg_access::{AlignmentHelper, NativeEndianess},
Expand Down Expand Up @@ -157,6 +158,10 @@ impl<'d> Aes<'d> {
ret
}

fn regs(&self) -> &pac::aes::RegisterBlock {
self.aes.register_block()
}

/// Encrypts/Decrypts the given buffer based on `mode` parameter
pub fn process<K>(&mut self, block: &mut [u8; 16], mode: Mode, key: K)
where
Expand Down Expand Up @@ -314,7 +319,7 @@ pub mod dma {

impl DmaSupport for AesDma<'_> {
fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
while self.aes.aes.state().read().state().bits() != 2 // DMA status DONE == 2
while self.aes.regs().state().read().state().bits() != 2 // DMA status DONE == 2
&& !self.channel.tx.is_done()
{
// wait until done
Expand Down Expand Up @@ -456,10 +461,10 @@ pub mod dma {

SYSTEM::regs()
.perip_rst_en1()
.modify(|_, w| w.crypto_aes_rst().set_bit());
.modify(|_, w| w.crypto_aes_rst().set_bit());
SYSTEM::regs()
.perip_rst_en1()
.modify(|_, w| w.crypto_aes_rst().clear_bit());
.modify(|_, w| w.crypto_aes_rst().clear_bit());
}

#[cfg(any(esp32c6, esp32h2))]
Expand All @@ -480,24 +485,24 @@ pub mod dma {

fn enable_dma(&self, enable: bool) {
self.aes
.aes
.regs()
.dma_enable()
.write(|w| w.dma_enable().bit(enable));
}

fn enable_interrupt(&self) {
self.aes.aes.int_ena().write(|w| w.int_ena().set_bit());
self.aes.regs().int_ena().write(|w| w.int_ena().set_bit());
}

fn set_cipher_mode(&self, mode: CipherMode) {
self.aes
.aes
.regs()
.block_mode()
.modify(|_, w| unsafe { w.block_mode().bits(mode as u8) });

if mode == CipherMode::Ctr {
self.aes
.aes
.regs()
.inc_sel()
.modify(|_, w| w.inc_sel().clear_bit());
}
Expand All @@ -508,14 +513,14 @@ pub mod dma {
}

fn finish_transform(&self) {
self.aes.aes.dma_exit().write(|w| w.dma_exit().set_bit());
self.aes.regs().dma_exit().write(|w| w.dma_exit().set_bit());
self.enable_dma(false);
self.reset_aes();
}

fn set_num_block(&self, block: u32) {
self.aes
.aes
.regs()
.block_num()
.modify(|_, w| unsafe { w.block_num().bits(block) });
}
Expand Down
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