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Replace pointer derefs with regs function (#2974)
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* Do not mix peripheral singletons with PAC types

* Replace pointer derefs with regs function
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@bugadani
bugadani authored Jan 20, 2025
1 parent 18ef297 commit 0894e30
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Showing 124 changed files with 1,937 additions and 2,410 deletions.
24 changes: 14 additions & 10 deletions esp-hal/src/aes/mod.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -452,22 +452,26 @@ pub mod dma {

#[cfg(any(esp32c3, esp32s2, esp32s3))]
fn reset_aes(&self) {
unsafe {
let s = crate::peripherals::SYSTEM::steal();
s.perip_rst_en1()
use crate::peripherals::SYSTEM;

SYSTEM::regs()
.perip_rst_en1()
.modify(|_, w| w.crypto_aes_rst().set_bit());
s.perip_rst_en1()
SYSTEM::regs()
.perip_rst_en1()
.modify(|_, w| w.crypto_aes_rst().clear_bit());
}
}

#[cfg(any(esp32c6, esp32h2))]
fn reset_aes(&self) {
unsafe {
let s = crate::peripherals::PCR::steal();
s.aes_conf().modify(|_, w| w.aes_rst_en().set_bit());
s.aes_conf().modify(|_, w| w.aes_rst_en().clear_bit());
}
use crate::peripherals::PCR;

PCR::regs()
.aes_conf()
.modify(|_, w| w.aes_rst_en().set_bit());
PCR::regs()
.aes_conf()
.modify(|_, w| w.aes_rst_en().clear_bit());
}

fn dma_peripheral(&self) -> DmaPeripheral {
Expand Down
50 changes: 25 additions & 25 deletions esp-hal/src/analog/adc/esp32.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,19 +49,19 @@ pub trait RegisterAccess {

impl RegisterAccess for ADC1 {
fn set_bit_width(resolution: u8) {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_start_force()
.modify(|_, w| unsafe { w.sar1_bit_width().bits(resolution) });
}

fn set_sample_bit(resolution: u8) {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_read_ctrl()
.modify(|_, w| unsafe { w.sar1_sample_bit().bits(resolution) });
}

fn set_attenuation(channel: usize, attenuation: u8) {
unsafe { &*SENS::ptr() }.sar_atten1().modify(|r, w| {
SENS::regs().sar_atten1().modify(|r, w| {
let new_value = (r.bits() & !(0b11 << (channel * 2)))
| (((attenuation & 0b11) as u32) << (channel * 2));

Expand All @@ -70,51 +70,51 @@ impl RegisterAccess for ADC1 {
}

fn clear_dig_force() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_read_ctrl()
.modify(|_, w| w.sar1_dig_force().clear_bit());
}

fn set_start_force() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start1()
.modify(|_, w| w.meas1_start_force().set_bit());
}

fn set_en_pad_force() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start1()
.modify(|_, w| w.sar1_en_pad_force().set_bit());
}

fn set_en_pad(channel: u8) {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start1()
.modify(|_, w| unsafe { w.sar1_en_pad().bits(1 << channel) });
}

fn clear_start_sar() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start1()
.modify(|_, w| w.meas1_start_sar().clear_bit());
}

fn set_start_sar() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start1()
.modify(|_, w| w.meas1_start_sar().set_bit());
}

fn read_done_sar() -> bool {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start1()
.read()
.meas1_done_sar()
.bit_is_set()
}

fn read_data_sar() -> u16 {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start1()
.read()
.meas1_data_sar()
Expand All @@ -124,19 +124,19 @@ impl RegisterAccess for ADC1 {

impl RegisterAccess for ADC2 {
fn set_bit_width(resolution: u8) {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_start_force()
.modify(|_, w| unsafe { w.sar2_bit_width().bits(resolution) });
}

fn set_sample_bit(resolution: u8) {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_read_ctrl2()
.modify(|_, w| unsafe { w.sar2_sample_bit().bits(resolution) });
}

fn set_attenuation(channel: usize, attenuation: u8) {
unsafe { &*SENS::ptr() }.sar_atten2().modify(|r, w| {
SENS::regs().sar_atten2().modify(|r, w| {
let new_value = (r.bits() & !(0b11 << (channel * 2)))
| (((attenuation & 0b11) as u32) << (channel * 2));

Expand All @@ -145,51 +145,51 @@ impl RegisterAccess for ADC2 {
}

fn clear_dig_force() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_read_ctrl2()
.modify(|_, w| w.sar2_dig_force().clear_bit());
}

fn set_start_force() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start2()
.modify(|_, w| w.meas2_start_force().set_bit());
}

fn set_en_pad_force() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start2()
.modify(|_, w| w.sar2_en_pad_force().set_bit());
}

fn set_en_pad(channel: u8) {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start2()
.modify(|_, w| unsafe { w.sar2_en_pad().bits(1 << channel) });
}

fn clear_start_sar() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start2()
.modify(|_, w| w.meas2_start_sar().clear_bit());
}

fn set_start_sar() {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start2()
.modify(|_, w| w.meas2_start_sar().set_bit());
}

fn read_done_sar() -> bool {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start2()
.read()
.meas2_done_sar()
.bit_is_set()
}

fn read_data_sar() -> u16 {
unsafe { &*SENS::ptr() }
SENS::regs()
.sar_meas_start2()
.read()
.meas2_data_sar()
Expand All @@ -214,7 +214,7 @@ where
adc_instance: impl crate::peripheral::Peripheral<P = ADCI> + 'd,
config: AdcConfig<ADCI>,
) -> Self {
let sensors = unsafe { &*SENS::ptr() };
let sensors = SENS::regs();

// Set reading and sampling resolution
let resolution: u8 = config.resolution as u8;
Expand Down Expand Up @@ -332,14 +332,14 @@ where
impl<ADC1> Adc<'_, ADC1> {
/// Enable the Hall sensor
pub fn enable_hall_sensor() {
unsafe { &*RTC_IO::ptr() }
RTC_IO::regs()
.hall_sens()
.modify(|_, w| w.xpd_hall().set_bit());
}

/// Disable the Hall sensor
pub fn disable_hall_sensor() {
unsafe { &*RTC_IO::ptr() }
RTC_IO::regs()
.hall_sens()
.modify(|_, w| w.xpd_hall().clear_bit());
}
Expand Down
56 changes: 23 additions & 33 deletions esp-hal/src/analog/adc/riscv.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -181,45 +181,40 @@ pub trait RegisterAccess {

impl RegisterAccess for crate::peripherals::ADC1 {
fn config_onetime_sample(channel: u8, attenuation: u8) {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.onetime_sample().modify(|_, w| unsafe {
APB_SARADC::regs().onetime_sample().modify(|_, w| unsafe {
w.saradc1_onetime_sample().set_bit();
w.onetime_channel().bits(channel);
w.onetime_atten().bits(attenuation)
});
}

fn start_onetime_sample() {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc
APB_SARADC::regs()
.onetime_sample()
.modify(|_, w| w.onetime_start().set_bit());
}

fn is_done() -> bool {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.int_raw().read().adc1_done().bit()
APB_SARADC::regs().int_raw().read().adc1_done().bit()
}

fn read_data() -> u16 {
let sar_adc = unsafe { &*APB_SARADC::PTR };

(sar_adc.sar1data_status().read().saradc1_data().bits() as u16) & 0xfff
APB_SARADC::regs()
.sar1data_status()
.read()
.saradc1_data()
.bits() as u16
& 0xfff
}

fn reset() {
let sar_adc = unsafe { &*APB_SARADC::PTR };

// Clear ADC1 sampling done interrupt bit
sar_adc
APB_SARADC::regs()
.int_clr()
.write(|w| w.adc1_done().clear_bit_by_one());

// Disable ADC sampling
sar_adc
APB_SARADC::regs()
.onetime_sample()
.modify(|_, w| w.onetime_start().clear_bit());
}
Expand Down Expand Up @@ -289,43 +284,38 @@ impl super::CalibrationAccess for crate::peripherals::ADC1 {
#[cfg(esp32c3)]
impl RegisterAccess for crate::peripherals::ADC2 {
fn config_onetime_sample(channel: u8, attenuation: u8) {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.onetime_sample().modify(|_, w| unsafe {
APB_SARADC::regs().onetime_sample().modify(|_, w| unsafe {
w.saradc2_onetime_sample().set_bit();
w.onetime_channel().bits(channel);
w.onetime_atten().bits(attenuation)
});
}

fn start_onetime_sample() {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc
APB_SARADC::regs()
.onetime_sample()
.modify(|_, w| w.onetime_start().set_bit());
}

fn is_done() -> bool {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.int_raw().read().adc2_done().bit()
APB_SARADC::regs().int_raw().read().adc2_done().bit()
}

fn read_data() -> u16 {
let sar_adc = unsafe { &*APB_SARADC::PTR };

(sar_adc.sar2data_status().read().saradc2_data().bits() as u16) & 0xfff
APB_SARADC::regs()
.sar2data_status()
.read()
.saradc2_data()
.bits() as u16
& 0xfff
}

fn reset() {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc
APB_SARADC::regs()
.int_clr()
.write(|w| w.adc2_done().clear_bit_by_one());

sar_adc
APB_SARADC::regs()
.onetime_sample()
.modify(|_, w| w.onetime_start().clear_bit());
}
Expand Down Expand Up @@ -413,7 +403,7 @@ where
) -> Self {
let guard = GenericPeripheralGuard::new();

unsafe { &*APB_SARADC::PTR }.ctrl().modify(|_, w| unsafe {
APB_SARADC::regs().ctrl().modify(|_, w| unsafe {
w.start_force().set_bit();
w.start().set_bit();
w.sar_clk_gated().set_bit();
Expand Down
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