add fast interrupt enable register

hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson

@@ -14,7 +14,7 @@
       swaccess: "ro",
       hwaccess: "hrw",
       fields: [
-        { bits: "15:0", name: "FAST_INTR_PENDING", desc: "Pending Fast Interrupt Reg" }
+        { bits: "14:0", name: "FAST_INTR_PENDING", desc: "Pending Fast Interrupt Reg" }
       ]
     }
 
@@ -24,9 +24,18 @@
       swaccess: "rw",
       hwaccess: "hrw",
       fields: [
-        { bits: "15:0", name: "FAST_INTR_CLEAR", desc: "Clear Fast Interrupt" }
+        { bits: "14:0", name: "FAST_INTR_CLEAR", desc: "Clear Fast Interrupt" }
       ]
     }
 
+    { name:     "FAST_INTR_ENABLE",
+      desc:     "Enable fast interrupt",
+      resval:   "0x7fff"
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "14:0", name: "FAST_INTR_ENABLE", desc: "Enable fast interrupt" }
+      ]
+    }
    ]
 }

hw/ip/fast_intr_ctrl/rtl/fast_intr_ctrl.sv

@@ -51,7 +51,7 @@ module fast_intr_ctrl #(
       end else begin
         if (fast_intr_i[i]) begin
           fast_intr_pending_de[i] = 1'b1;
-          hw2reg.fast_intr_pending.d[i] = 1'b1;
+          hw2reg.fast_intr_pending.d[i] = reg2hw.fast_intr_enable.q[i];
           fast_intr_clear_de[i] = 1'b0;
           hw2reg.fast_intr_clear.d[i] = 1'b0;
         end else begin
@@ -65,9 +65,7 @@ module fast_intr_ctrl #(
 
   end
 
-  assign hw2reg.fast_intr_pending.d[15] = 1'b0;
-  assign hw2reg.fast_intr_clear.d[15] = 1'b0;
-  assign fast_intr_o = reg2hw.fast_intr_pending.q[14:0];
+  assign fast_intr_o = reg2hw.fast_intr_pending.q;
   assign hw2reg.fast_intr_pending.de = |fast_intr_pending_de;
   assign hw2reg.fast_intr_clear.de = |fast_intr_clear_de;
 

hw/ip/fast_intr_ctrl/rtl/fast_intr_ctrl_reg_pkg.sv

@@ -7,52 +7,58 @@
 package fast_intr_ctrl_reg_pkg;
 
   // Address widths within the block
-  parameter int BlockAw = 3;
+  parameter int BlockAw = 4;
 
   ////////////////////////////
   // Typedefs for registers //
   ////////////////////////////
 
-  typedef struct packed {logic [15:0] q;} fast_intr_ctrl_reg2hw_fast_intr_pending_reg_t;
+  typedef struct packed {logic [14:0] q;} fast_intr_ctrl_reg2hw_fast_intr_pending_reg_t;
 
-  typedef struct packed {logic [15:0] q;} fast_intr_ctrl_reg2hw_fast_intr_clear_reg_t;
+  typedef struct packed {logic [14:0] q;} fast_intr_ctrl_reg2hw_fast_intr_clear_reg_t;
+
+  typedef struct packed {logic [14:0] q;} fast_intr_ctrl_reg2hw_fast_intr_enable_reg_t;
 
   typedef struct packed {
-    logic [15:0] d;
+    logic [14:0] d;
     logic        de;
   } fast_intr_ctrl_hw2reg_fast_intr_pending_reg_t;
 
   typedef struct packed {
-    logic [15:0] d;
+    logic [14:0] d;
     logic        de;
   } fast_intr_ctrl_hw2reg_fast_intr_clear_reg_t;
 
   // Register -> HW type
   typedef struct packed {
-    fast_intr_ctrl_reg2hw_fast_intr_pending_reg_t fast_intr_pending;  // [31:16]
-    fast_intr_ctrl_reg2hw_fast_intr_clear_reg_t   fast_intr_clear;    // [15:0]
+    fast_intr_ctrl_reg2hw_fast_intr_pending_reg_t fast_intr_pending;  // [44:30]
+    fast_intr_ctrl_reg2hw_fast_intr_clear_reg_t   fast_intr_clear;    // [29:15]
+    fast_intr_ctrl_reg2hw_fast_intr_enable_reg_t  fast_intr_enable;   // [14:0]
   } fast_intr_ctrl_reg2hw_t;
 
   // HW -> register type
   typedef struct packed {
-    fast_intr_ctrl_hw2reg_fast_intr_pending_reg_t fast_intr_pending;  // [33:17]
-    fast_intr_ctrl_hw2reg_fast_intr_clear_reg_t   fast_intr_clear;    // [16:0]
+    fast_intr_ctrl_hw2reg_fast_intr_pending_reg_t fast_intr_pending;  // [31:16]
+    fast_intr_ctrl_hw2reg_fast_intr_clear_reg_t   fast_intr_clear;    // [15:0]
   } fast_intr_ctrl_hw2reg_t;
 
   // Register offsets
-  parameter logic [BlockAw-1:0] FAST_INTR_CTRL_FAST_INTR_PENDING_OFFSET = 3'h0;
-  parameter logic [BlockAw-1:0] FAST_INTR_CTRL_FAST_INTR_CLEAR_OFFSET = 3'h4;
+  parameter logic [BlockAw-1:0] FAST_INTR_CTRL_FAST_INTR_PENDING_OFFSET = 4'h0;
+  parameter logic [BlockAw-1:0] FAST_INTR_CTRL_FAST_INTR_CLEAR_OFFSET = 4'h4;
+  parameter logic [BlockAw-1:0] FAST_INTR_CTRL_FAST_INTR_ENABLE_OFFSET = 4'h8;
 
   // Register index
   typedef enum int {
     FAST_INTR_CTRL_FAST_INTR_PENDING,
-    FAST_INTR_CTRL_FAST_INTR_CLEAR
+    FAST_INTR_CTRL_FAST_INTR_CLEAR,
+    FAST_INTR_CTRL_FAST_INTR_ENABLE
   } fast_intr_ctrl_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] FAST_INTR_CTRL_PERMIT[2] = '{
+  parameter logic [3:0] FAST_INTR_CTRL_PERMIT[3] = '{
       4'b0011,  // index[0] FAST_INTR_CTRL_FAST_INTR_PENDING
-      4'b0011  // index[1] FAST_INTR_CTRL_FAST_INTR_CLEAR
+      4'b0011,  // index[1] FAST_INTR_CTRL_FAST_INTR_CLEAR
+      4'b0011  // index[2] FAST_INTR_CTRL_FAST_INTR_ENABLE
   };
 
 endpackage

hw/ip/fast_intr_ctrl/rtl/fast_intr_ctrl_reg_top.sv

@@ -10,10 +10,10 @@
 module fast_intr_ctrl_reg_top #(
     parameter type reg_req_t = logic,
     parameter type reg_rsp_t = logic,
-    parameter int AW = 3
+    parameter int AW = 4
 ) (
-    input clk_i,
-    input rst_ni,
+    input logic clk_i,
+    input logic rst_ni,
     input reg_req_t reg_req_i,
     output reg_rsp_t reg_rsp_o,
     // To HW
@@ -68,18 +68,21 @@ module fast_intr_ctrl_reg_top #(
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}
   //        or <reg>_{wd|we|qs} if field == 1 or 0
-  logic [15:0] fast_intr_pending_qs;
-  logic [15:0] fast_intr_clear_qs;
-  logic [15:0] fast_intr_clear_wd;
+  logic [14:0] fast_intr_pending_qs;
+  logic [14:0] fast_intr_clear_qs;
+  logic [14:0] fast_intr_clear_wd;
   logic fast_intr_clear_we;
+  logic [14:0] fast_intr_enable_qs;
+  logic [14:0] fast_intr_enable_wd;
+  logic fast_intr_enable_we;
 
   // Register instances
   // R[fast_intr_pending]: V(False)
 
   prim_subreg #(
-      .DW      (16),
+      .DW      (15),
       .SWACCESS("RO"),
-      .RESVAL  (16'h0)
+      .RESVAL  (15'h0)
   ) u_fast_intr_pending (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
@@ -103,9 +106,9 @@ module fast_intr_ctrl_reg_top #(
   // R[fast_intr_clear]: V(False)
 
   prim_subreg #(
-      .DW      (16),
+      .DW      (15),
       .SWACCESS("RW"),
-      .RESVAL  (16'h0)
+      .RESVAL  (15'h0)
   ) u_fast_intr_clear (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
@@ -127,13 +130,41 @@ module fast_intr_ctrl_reg_top #(
   );
 
 
+  // R[fast_intr_enable]: V(False)
+
+  prim_subreg #(
+      .DW      (15),
+      .SWACCESS("RW"),
+      .RESVAL  (15'h7fff)
+  ) u_fast_intr_enable (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(fast_intr_enable_we),
+      .wd(fast_intr_enable_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.fast_intr_enable.q),
+
+      // to register interface (read)
+      .qs(fast_intr_enable_qs)
+  );
 
 
-  logic [1:0] addr_hit;
+
+
+  logic [2:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[0] = (reg_addr == FAST_INTR_CTRL_FAST_INTR_PENDING_OFFSET);
     addr_hit[1] = (reg_addr == FAST_INTR_CTRL_FAST_INTR_CLEAR_OFFSET);
+    addr_hit[2] = (reg_addr == FAST_INTR_CTRL_FAST_INTR_ENABLE_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0;
@@ -142,22 +173,30 @@ module fast_intr_ctrl_reg_top #(
   always_comb begin
     wr_err = (reg_we &
               ((addr_hit[0] & (|(FAST_INTR_CTRL_PERMIT[0] & ~reg_be))) |
-               (addr_hit[1] & (|(FAST_INTR_CTRL_PERMIT[1] & ~reg_be)))));
+               (addr_hit[1] & (|(FAST_INTR_CTRL_PERMIT[1] & ~reg_be))) |
+               (addr_hit[2] & (|(FAST_INTR_CTRL_PERMIT[2] & ~reg_be)))));
   end
 
-  assign fast_intr_clear_we = addr_hit[1] & reg_we & !reg_error;
-  assign fast_intr_clear_wd = reg_wdata[15:0];
+  assign fast_intr_clear_we  = addr_hit[1] & reg_we & !reg_error;
+  assign fast_intr_clear_wd  = reg_wdata[14:0];
+
+  assign fast_intr_enable_we = addr_hit[2] & reg_we & !reg_error;
+  assign fast_intr_enable_wd = reg_wdata[14:0];
 
   // Read data return
   always_comb begin
     reg_rdata_next = '0;
     unique case (1'b1)
       addr_hit[0]: begin
-        reg_rdata_next[15:0] = fast_intr_pending_qs;
+        reg_rdata_next[14:0] = fast_intr_pending_qs;
       end
 
       addr_hit[1]: begin
-        reg_rdata_next[15:0] = fast_intr_clear_qs;
+        reg_rdata_next[14:0] = fast_intr_clear_qs;
+      end
+
+      addr_hit[2]: begin
+        reg_rdata_next[14:0] = fast_intr_enable_qs;
       end
 
       default: begin

sw/applications/dma_example/main.c

@@ -47,6 +47,9 @@ void fic_irq_dma(void)
 
 int main(int argc, char *argv[])
 {
+    enable_all_fast_interrupts(true); // not needed is default - done on reset
+
+
     printf("--- DMA EXAMPLE ---\n");
 
     // Enable interrupt on processor side
@@ -189,5 +192,8 @@ int main(int argc, char *argv[])
         }
     #endif // TEST_BYTE
 
+    enable_fast_interrupt(kDma_fic_e, false);
+    dma_set_cnt_start(&dma, 4); // restart to test
+
     return EXIT_SUCCESS;
 }

sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.c

@@ -202,6 +202,23 @@ INTERRUPT_HANDLER_ABI void handler_irq_fast_gpio_7(void);
 /*                           EXPORTED FUNCTIONS                             */
 /**                                                                        **/
 /****************************************************************************/
+fast_intr_ctrl_result_t enable_fast_interrupt(fast_intr_ctrl_fast_interrupt_t\
+ fast_interrupt, bool enable) 
+{
+    /* masking a 32b go write in reg*/
+    uint32_t reg = fast_intr_ctrl_peri->FAST_INTR_ENABLE;
+    reg = bitfield_bit32_write(reg, fast_interrupt, enable);
+    /* write in reg through structure */
+    fast_intr_ctrl_peri->FAST_INTR_ENABLE = reg;
+    return kFastIntrCtrlOk_e;
+}
+
+fast_intr_ctrl_result_t enable_all_fast_interrupts(bool enable) 
+{
+    fast_intr_ctrl_peri->FAST_INTR_ENABLE = enable ? 0x7fff : 0x0000;
+    return kFastIntrCtrlOk_e;
+}
+
 
 fast_intr_ctrl_result_t clear_fast_interrupt(fast_intr_ctrl_fast_interrupt_t\
  fast_interrupt)

sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.h

@@ -93,6 +93,27 @@ typedef enum fast_intr_ctrl_fast_interrupt {
 /**                                                                        **/
 /****************************************************************************/
 
+/**
+ * @brief Enable the generation of the fast interrupt
+ * peripheral by writing inside FAST_INTR_ENABLE
+ * @param fast_interrupt specify the peripheral that will be enabled
+ * @param enable enable value
+ * @retval kFastIntrCtrlOk_e (= 0) if successfully set the bit
+ * @retval kFastIntrCtrlError_e (= 1) if an error occured during operation
+ */
+fast_intr_ctrl_result_t enable_fast_interrupt(fast_intr_ctrl_fast_interrupt_t\
+ fast_interrupt, bool enable);
+
+ /**
+ * @brief Enable the generation of the fast interrupt
+ * peripheral by writing inside FAST_INTR_ENABLE
+ * @param enable enable value
+ * @retval kFastIntrCtrlOk_e (= 0) if successfully set the bit
+ * @retval kFastIntrCtrlError_e (= 1) if an error occured during operation
+ */
+fast_intr_ctrl_result_t enable_all_fast_interrupts(bool enable);
+
+
 /**
  * @brief clean the bit inside FAST_INTR_PENDING register for the requested 
  * peripheral by writing inside FAST_INTR_CLEAR

sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl_regs.h

@@ -18,18 +18,25 @@ extern "C" {
 
 // Pending fast interrupt
 #define FAST_INTR_CTRL_FAST_INTR_PENDING_REG_OFFSET 0x0
-#define FAST_INTR_CTRL_FAST_INTR_PENDING_FAST_INTR_PENDING_MASK 0xffff
+#define FAST_INTR_CTRL_FAST_INTR_PENDING_FAST_INTR_PENDING_MASK 0x7fff
 #define FAST_INTR_CTRL_FAST_INTR_PENDING_FAST_INTR_PENDING_OFFSET 0
 #define FAST_INTR_CTRL_FAST_INTR_PENDING_FAST_INTR_PENDING_FIELD \
   ((bitfield_field32_t) { .mask = FAST_INTR_CTRL_FAST_INTR_PENDING_FAST_INTR_PENDING_MASK, .index = FAST_INTR_CTRL_FAST_INTR_PENDING_FAST_INTR_PENDING_OFFSET })
 
 // Clear fast interrupt
 #define FAST_INTR_CTRL_FAST_INTR_CLEAR_REG_OFFSET 0x4
-#define FAST_INTR_CTRL_FAST_INTR_CLEAR_FAST_INTR_CLEAR_MASK 0xffff
+#define FAST_INTR_CTRL_FAST_INTR_CLEAR_FAST_INTR_CLEAR_MASK 0x7fff
 #define FAST_INTR_CTRL_FAST_INTR_CLEAR_FAST_INTR_CLEAR_OFFSET 0
 #define FAST_INTR_CTRL_FAST_INTR_CLEAR_FAST_INTR_CLEAR_FIELD \
   ((bitfield_field32_t) { .mask = FAST_INTR_CTRL_FAST_INTR_CLEAR_FAST_INTR_CLEAR_MASK, .index = FAST_INTR_CTRL_FAST_INTR_CLEAR_FAST_INTR_CLEAR_OFFSET })
 
+// Enable fast interrupt
+#define FAST_INTR_CTRL_FAST_INTR_ENABLE_REG_OFFSET 0x8
+#define FAST_INTR_CTRL_FAST_INTR_ENABLE_FAST_INTR_ENABLE_MASK 0x7fff
+#define FAST_INTR_CTRL_FAST_INTR_ENABLE_FAST_INTR_ENABLE_OFFSET 0
+#define FAST_INTR_CTRL_FAST_INTR_ENABLE_FAST_INTR_ENABLE_FIELD \
+  ((bitfield_field32_t) { .mask = FAST_INTR_CTRL_FAST_INTR_ENABLE_FAST_INTR_ENABLE_MASK, .index = FAST_INTR_CTRL_FAST_INTR_ENABLE_FAST_INTR_ENABLE_OFFSET })
+
 #ifdef __cplusplus
 }  // extern "C"
 #endif