Cleaning up flags (#316)

* by default USE_EXTERNAL_DEVICE_EXAMPLE * moved UPF flag to parameter * moved to param more flags * Update README.md
esl-epfl · Jun 22, 2023 · e2156d1 · e2156d1
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diff --git a/Debug.md b/Debug.md
@@ -40,10 +40,10 @@ The remote bitbang server is simplemented in the folder ./hw/vendor/pulp_platfor
 
 ### Verilator
 
-To simulate your application with Questasim using the remote_bitbang server, you need to compile you system adding the flag `use_jtag_dpi`:
+To simulate your application with Questasim using the remote_bitbang server, you need to compile you system adding the `JTAG DPI` functions:
 
 ```
-make verilator-sim FUSESOC_FLAGS="--flag use_jtag_dpi"
+make verilator-sim "FUSESOC_PARAM="--JTAG_DPI=1"
 ```
 
 then, go to your target system built folder
@@ -60,10 +60,10 @@ and type to run your compiled software:
 
 ### Questasim
 
-To simulate your application with Questasim using the remote_bitbang server, you need to compile you system adding the flag `use_jtag_dpi`:
+To simulate your application with Questasim using the remote_bitbang server, you need to compile you system adding the `JTAG DPI` functions:
 
 ```
-make questasim-sim FUSESOC_FLAGS="--flag=use_jtag_dpi"
+make questasim-sim "FUSESOC_PARAM="--JTAG_DPI=1"
 ```
 
 then, go to your target system built folder

diff --git a/ExecuteFromFlash.md b/ExecuteFromFlash.md
@@ -45,7 +45,7 @@ Then it loads the `boot_address` from a memory-mapped register that is set to
 0x180 at reset time, which is also the boot address specified in the entry point of the 
 linked scripts.
 If you want to simulate the actual JTAG procedure without pre-loading instead, 
-compile the RTL with the `use_jtag_dpi` flag and follow the `Debug.md` guide.
+compile the RTL with the `FUSESOC_PARAM="--JTAG_DPI=1"` flag and follow the `Debug.md` guide.
 
 ### SPI Flash Execution Boot Procedure
 
@@ -72,10 +72,6 @@ To use this mode, when targetting ASICs or FPGA bitstreams,
 make sure you have the `boot_sel_i` input (e.g., a switch) set to 1, 
 and the `execute_from_flash_i` set to 1 too.
 
-To simulate this procedure, you must compile the RTL 
-with the `use_external_device_example` flag to 
-tell fusesoc to compile the FLASH model.
-
 Note that the FLASH model is not compatible with **verilator**, 
 thus the simulation must be carried out with either **modelsim** or **vcs**.
 

diff --git a/ExternalDevices.md b/ExternalDevices.md
@@ -28,12 +28,12 @@ To run the external device example, first compile the software example:
 make app PROJECT=example_external_peripheral
 ```
 
-By default, the external device example RTL code is disabled. Run fusesoc with the '--flag=use_external_device_example' option to enable it. This example is available for the sim and sim_opt targets.
+By default, the external device example RTL code is disabled. This example is available for the sim and sim_opt targets.
 
 For example, compile for Verilator with:
 
 ```
-make verilator-sim FUSESOC_FLAGS="--flag=use_external_device_example"
+make verilator-sim
 ```
 
 then, go to your target system built folder

diff --git a/Makefile b/Makefile
@@ -130,30 +130,30 @@ app-compile-all:
 
 ## Verilator simulation
 verilator-sim:
-	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --setup --build openhwgroup.org:systems:core-v-mini-mcu 2>&1 | tee buildsim.log
+	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
 
 ## Questasim simulation
 questasim-sim:
-	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --setup --build openhwgroup.org:systems:core-v-mini-mcu 2>&1 | tee buildsim.log
+	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
 
 ## Questasim simulation with HDL optimized compilation
 questasim-sim-opt: questasim-sim
 	$(MAKE) -C build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-modelsim opt
 
 ## Questasim simulation with HDL optimized compilation and UPF power domain description
-## @param FUSESOC_FLAGS="--flag=use_upf"
+## @param FUSESOC_PARAM="--USE_UPF"
 questasim-sim-opt-upf: questasim-sim
 	$(MAKE) -C build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-modelsim opt-upf
 
 ## Verilator simulation
 ## @param CPU=cv32e20(default),cv32e40p,cv32e40x
 ## @param BUS=onetoM(default),NtoM
 vcs-sim:
-	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=vcs $(FUSESOC_FLAGS) --setup --build openhwgroup.org:systems:core-v-mini-mcu 2>&1 | tee buildsim.log
+	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=vcs $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
 
 ## VCS-AMS simulation:
 vcs-ams-sim:
-	$(FUSESOC) --cores-root . run --no-export --target=sim --flag "ams_sim" --flag "use_external_device_example" --tool=vcs $(FUSESOC_FLAGS) --setup --build openhwgroup.org:systems:core-v-mini-mcu 2>&1 | tee buildsim.log
+	$(FUSESOC) --cores-root . run --no-export --target=sim --flag "ams_sim" --tool=vcs $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
 
 ## Generates the build output for helloworld application
 ## Uses verilator to simulate the HW model and run the FW
@@ -189,20 +189,20 @@ run-app-sim:
 ## @param FPGA_BOARD=nexys-a7-100t,pynq-z2
 ## @param FUSESOC_FLAGS=--flag=<flagname>
 vivado-fpga:
-	$(FUSESOC) --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup --build openhwgroup.org:systems:core-v-mini-mcu 2>&1 | tee buildvivado.log
+	$(FUSESOC) --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildvivado.log
 
 vivado-fpga-nobuild:
-	$(FUSESOC) --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup openhwgroup.org:systems:core-v-mini-mcu 2>&1 | tee buildvivado.log
+	$(FUSESOC) --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildvivado.log
 
 ## @section ASIC
 ## Note that for this step you need to provide technology-dependent files (e.g., libs, constraints)
 asic:
-	$(FUSESOC) --cores-root . run --no-export --target=asic_synthesis --setup openhwgroup.org:systems:core-v-mini-mcu 2>&1 | tee builddesigncompiler.log
+	$(FUSESOC) --cores-root . run --no-export --target=asic_synthesis --setup openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee builddesigncompiler.log
 
 openroad-sky130:
 	git checkout hw/vendor/pulp_platform_common_cells/*
 	sed -i 's/(\*[^\n]*\*)//g' hw/vendor/pulp_platform_common_cells/src/*.sv
-	$(FUSESOC) --verbose --cores-root . run --target=asic_yosys_synthesis --flag=use_sky130 openhwgroup.org:systems:core-v-mini-mcu 2>&1 | tee buildopenroad.log
+	$(FUSESOC) --verbose --cores-root . run --target=asic_yosys_synthesis --flag=use_sky130 openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildopenroad.log
 	git checkout hw/vendor/pulp_platform_common_cells/*
 
 

diff --git a/README.md b/README.md
@@ -251,7 +251,7 @@ Moreover, FreeRTOS is being fetch from 'https://github.com/FreeRTOS/FreeRTOS-Ker
 This project supports simulation with Verilator, Synopsys VCS, and Siemens Questasim.
 It relies on `fusesoc` to handle multiple EDA tools and parameters.
 For example, if you want to set the `FPU` and `COREV_PULP` parameters of the `cv32e40p` CPU,
-you need to add next to your compilation command `FUSESOC_FLAGS="--flag=use_cv32e40p_corev_pulp --flag=use_cv32e40p_fpu"`
+you need to add next to your compilation command `FUSESOC_PARAM="--COREV_PULP=1 --FPU=1"`
 Below the different EDA examples commands.
 
 ### Compiling for Verilator
@@ -363,7 +363,7 @@ make run RUN_OPT=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
 You can also compile with the UPF power domain description as:
 
 ```
-make questasim-sim-opt-upf FUSESOC_FLAGS="--flag=use_upf"
+make questasim-sim-opt-upf FUSESOC_PARAM="--USE_UPF"
 ```
 
 and then execute software as:

diff --git a/core-v-mini-mcu.core b/core-v-mini-mcu.core
@@ -211,23 +211,32 @@ parameters:
   COREV_PULP:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables COREV_PULP custom RISC-V extension on the CV32E40P core. Admitted values: 1|0.
     default: 0
   FPU:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables RV32F RISC-V extension on the CV32E40P core. Admitted values: 1|0.
     default: 0
   JTAG_DPI:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables testbench JTAG DIPs. Admitted values: 1|0.
     default: 0
   USE_EXTERNAL_DEVICE_EXAMPLE:
-    datatype: bool
-    paramtype: vlogdefine
-    default: false
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables testbench modules compilation. Admitted values: 1|0.
+    default: 1
   USE_UPF:
     datatype: bool
     paramtype: vlogdefine
-    default: false
+    description: |
+      Enables simulation with UPF with Modelsim/VCS
   SYNTHESIS:
     datatype: bool
     paramtype: vlogdefine
@@ -303,14 +312,11 @@ targets:
         - tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
         - ams_sim? (pre_patch_vcs_ams_Makefile)
     parameters:
-    - use_cv32e40p_corev_pulp? (COREV_PULP=1)
-    - "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
-    - use_cv32e40p_fpu? (FPU=1)
-    - "!use_cv32e40p_fpu? (FPU=0)"
-    - use_jtag_dpi? (JTAG_DPI=1)
-    - "!use_jtag_dpi? (JTAG_DPI=0)"
-    - use_external_device_example? (USE_EXTERNAL_DEVICE_EXAMPLE=true)
-    - use_upf? (USE_UPF=true)
+    - COREV_PULP
+    - FPU
+    - JTAG_DPI
+    - USE_EXTERNAL_DEVICE_EXAMPLE
+    - USE_UPF
     tools:
       modelsim:
         vlog_options:
@@ -364,10 +370,8 @@ targets:
     - ip-fpga
     - xdc-fpga-nexys
     parameters:
-    - use_cv32e40p_corev_pulp? (COREV_PULP=1)
-    - "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
-    - use_cv32e40p_fpu? (FPU=1)
-    - "!use_cv32e40p_fpu? (FPU=0)"
+    - COREV_PULP
+    - FPU
     - SYNTHESIS=true
     tools:
       vivado:
@@ -384,10 +388,8 @@ targets:
     - ip-fpga
     - xdc-fpga-pynq-z2
     parameters:
-    - use_cv32e40p_corev_pulp? (COREV_PULP=1)
-    - "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
-    - use_cv32e40p_fpu? (FPU=1)
-    - "!use_cv32e40p_fpu? (FPU=0)"
+    - COREV_PULP
+    - FPU
     - SYNTHESIS=true
     tools:
       vivado:
@@ -404,10 +406,8 @@ targets:
     - ip-fpga
     - fpga-arm-emulation
     parameters:
-    - use_cv32e40p_corev_pulp? (COREV_PULP=1)
-    - "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
-    - use_cv32e40p_fpu? (FPU=1)
-    - "!use_cv32e40p_fpu? (FPU=0)"
+    - COREV_PULP
+    - FPU
     - SYNTHESIS=true
     tools:
       vivado:
@@ -424,10 +424,8 @@ targets:
     hooks:
       post_build: [post_build_modelsim_scripts]
     parameters:
-    - use_cv32e40p_corev_pulp? (COREV_PULP=1)
-    - "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
-    - use_cv32e40p_fpu? (FPU=1)
-    - "!use_cv32e40p_fpu? (FPU=0)"
+    - COREV_PULP
+    - FPU
     - FPGA_NETLIST=true
     tools:
       modelsim:
@@ -442,10 +440,8 @@ targets:
     default_tool: design_compiler
     description: Design Compiler Script
     parameters:
-    - use_cv32e40p_corev_pulp? (COREV_PULP=1)
-    - "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
-    - use_cv32e40p_fpu? (FPU=1)
-    - "!use_cv32e40p_fpu? (FPU=0)"
+    - COREV_PULP
+    - FPU
     - SYNTHESIS=true
     filesets_append:
     - ip-asic
@@ -466,10 +462,8 @@ targets:
     default_tool: openroad
     description: yosys
     parameters:
-      - use_cv32e40p_corev_pulp? (COREV_PULP=1)
-      - "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
-      - use_cv32e40p_fpu? (FPU=1)
-      - "!use_cv32e40p_fpu? (FPU=0)"
+      - COREV_PULP
+      - FPU
       - SYNTHESIS=true
       - VERILATOR=true
     filesets_append:

diff --git a/eXtendingHEEP.md b/eXtendingHEEP.md
@@ -141,22 +141,19 @@ To add this new top-level module to the simulation/synthesis flow you can extend
         file_type: user
 
     parameters:
-    PULP_XPULP:
+    COREV_PULP:
         datatype: int
         paramtype: vlogparam
         default: 0
     JTAG_DPI:
         datatype: int
         paramtype: vlogparam
         default: 0
-    USE_EXTERNAL_DEVICE_EXAMPLE:
-        datatype: bool
-        paramtype: vlogdefine
-        default: false
     USE_UPF:
-        datatype: bool
-        paramtype: vlogdefine
-        default: false
+      datatype: bool
+      paramtype: vlogdefine
+      description: |
+        Enables simulation with UPF with Modelsim/VCS
 
     scripts:
     pre_build_remote_bitbang:
@@ -193,11 +190,8 @@ To add this new top-level module to the simulation/synthesis flow you can extend
             - tool_modelsim? (pre_build_remote_bitbang)
             - tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
         parameters:
-        - PULP_XPULP=0
-        - use_jtag_dpi? (JTAG_DPI=1)
-        - "!use_jtag_dpi? (JTAG_DPI=0)"
-        - use_external_device_example? (USE_EXTERNAL_DEVICE_EXAMPLE=true)
-        - use_upf? (USE_UPF=true)
+        - COREV_PULP
+        - JTAG_DPI
         tools:
         modelsim:
             vlog_options:

diff --git a/run_verif.sh b/run_verif.sh
@@ -8,7 +8,7 @@ if [[ $1 = "rtl" ]]
 then
     type="rtl"
     fusesoc="questasim-sim-opt-upf"
-    fusesoc_flags="--flag=use_upf --flag=use_external_device_example"
+    fusesoc_flags="--flag=use_upf"
     sim_folder="sim-modelsim"
     upf="RUN_UPF=1"
 else

diff --git a/sw/applications/i2s/main.c b/sw/applications/i2s/main.c
@@ -308,7 +308,7 @@ int main(int argc, char *argv[]) {
     }
 
     if (! mic_connected) {
-        printf("WARNING: Please build with `make verilator-sim FUSESOC_FLAGS=\"--flag=use_external_device_example\"\r\n");
+        printf("WARNING: Microphone not connected!\r\n");
     }
 #endif
     i2s_terminate();

diff --git a/tb/tb_top.sv b/tb/tb_top.sv
@@ -3,10 +3,11 @@
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 module tb_top #(
-    parameter COREV_PULP = 0,
-    parameter FPU        = 0,
-    parameter ZFINX      = 0,
-    parameter JTAG_DPI   = 0
+    parameter COREV_PULP                  = 0,
+    parameter FPU                         = 0,
+    parameter ZFINX                       = 0,
+    parameter JTAG_DPI                    = 0,
+    parameter USE_EXTERNAL_DEVICE_EXAMPLE = 1
 );
 
   // comment to record execution trace
@@ -189,11 +190,12 @@ module tb_top #(
 
   // wrapper for riscv, the memory system and stdout peripheral
   testharness #(
-      .COREV_PULP   (COREV_PULP),
-      .FPU          (FPU),
-      .ZFINX        (ZFINX),
-      .JTAG_DPI     (JTAG_DPI),
-      .CLK_FREQUENCY(CLK_FREQUENCY_KHz)
+      .COREV_PULP                 (COREV_PULP),
+      .FPU                        (FPU),
+      .ZFINX                      (ZFINX),
+      .JTAG_DPI                   (JTAG_DPI),
+      .USE_EXTERNAL_DEVICE_EXAMPLE(USE_EXTERNAL_DEVICE_EXAMPLE),
+      .CLK_FREQUENCY              (CLK_FREQUENCY_KHz)
   ) testharness_i (
       .clk_i               (clk_w),
       .rst_ni              (rst_n_w),