code cleaning

enjoy-digital · Jan 16, 2020 · 509076c · 509076c
1 parent 85cc027
commit 509076c
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diff --git a/litex/soc/cores/cpu/blackparrot/README.md b/litex/soc/cores/cpu/blackparrot/README.md
@@ -3,10 +3,9 @@ git submodule update --init --recursive (for blackparrot pre-alpha repo)
 cd pre_alpha_release
 follow getting_started to install blackparrot
 cd ..
-source ./setEnvironment.sh #required before running build_dut.sh
+source ./setEnvironment.sh #should be sourced each time you open a terminal or just add this line to bashrc
 Add $BP_TOP/external/bin to $PATH for verilator and riscv-gnu tools
-
-
+./update_BP.sh #to modify some of the files in Blackparrot repo (one-time process)
 Currently, we could simulate the LITEX-BIOS on BP processor. 
 
 [![asciicast](https://asciinema.org/a/286568.svg)](https://asciinema.org/a/286568)

diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/.bp2wb_convertor.v.swp b/litex/soc/cores/cpu/blackparrot/bp_fpga/.bp2wb_convertor.v.swp
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
@@ -20,7 +20,7 @@ module ExampleBlackParrotSystem
    // Tracing parameters
    , parameter calc_trace_p                = 1
    , parameter cce_trace_p                 = 0
-   , parameter cmt_trace_p                 = 1
+   , parameter cmt_trace_p                 = 0
    , parameter dram_trace_p                = 0
    , parameter skip_init_p                 = 0
 
@@ -171,7 +171,7 @@ bp_chip
        );
 
 
-/*  bind bp_be_top
+  bind bp_be_top
     bp_be_nonsynth_tracer
      #(.cfg_p(cfg_p))
      tracer
@@ -207,7 +207,7 @@ bp_chip
        ,.priv_mode_i(be_mem.csr.priv_mode_n)
        ,.mpp_i(be_mem.csr.mstatus_n.mpp)
        );
-*/
+
 /*bind bp_be_top
   bp_be_nonsynth_perf
    #(.cfg_p(cfg_p))

diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v
@@ -25,7 +25,7 @@ module bp2wb_convertor
    , localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity
    , localparam total_datafetch_cycle_lp   = cce_block_width_p / wbone_data_width
    , localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp)
-   , localparam cached_addr_base =  32'h5000_0000
+   , localparam cached_addr_base =  32'h4000_4000//   32'h5000_0000
    )
   (input                                 clk_i
    ,(* mark_debug = "true" *) input                               reset_i

diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor_v2.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor_v2.v
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v
@@ -0,0 +1,55 @@
+/*
+* bsg_mem_1rw_sync_mask_write_bit.v
+*
+* distributed synchronous 1-port ram for xilinx ultrascale or ultrascale plus FPGA
+* Write mode: No-change | Read mode: No-change
+* Note:
+* There are 2 basic BRAM library primitives, RAMB18E2 and RAMB36E2 in Vivado.
+* But none of them support bit-wise mask. They have Byte-wide write enable ports though.
+* So we use the RAM_STYLE attribute to instruct the tool to infer distributed LUT RAM instead.
+*
+* To save resources, the code is written to be inferred as Signle-port distributed ram RAM64X1S.
+* https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf
+*
+*/
+
+
+module bsg_mem_1rw_sync_mask_write_bit #(
+  parameter width_p = "inv"
+  , parameter els_p = "inv"
+  , parameter latch_last_read_p=0
+  , parameter enable_clock_gating_p=0
+  , localparam addr_width_lp = `BSG_SAFE_CLOG2(els_p)
+) (
+  input                      clk_i
+  , input                      reset_i
+  , input  [      width_p-1:0] data_i
+  , input  [addr_width_lp-1:0] addr_i
+  , input                      v_i
+  , input  [      width_p-1:0] w_mask_i
+  , input                      w_i
+  , output [      width_p-1:0] data_o
+);
+
+  wire unused = reset_i;
+
+  (* ram_style = "distributed" *) logic [width_p-1:0] mem [els_p-1:0];
+
+  logic [width_p-1:0] data_r;
+  always_ff @(posedge clk_i) begin
+    if (v_i & ~w_i)
+      data_r <= mem[addr_i];
+  end
+
+  assign data_o = data_r;
+
+  for (genvar i=0; i<width_p; i=i+1) begin
+    always_ff @(posedge clk_i) begin
+      if (v_i)
+        if (w_i & w_mask_i[i])
+          mem[addr_i][i] <= data_i[i];
+    end
+  end
+
+endmodule
+