BlackParrot initial commit

.gitmodules

@@ -22,3 +22,6 @@
 [submodule "litex/soc/cores/cpu/rocket/verilog"]
 	path = litex/soc/cores/cpu/rocket/verilog
 	url = https://github.com/enjoy-digital/rocket-litex-verilog
+[submodule "litex/soc/cores/cpu/blackparrot/pre-alpha-release"]
+	path = litex/soc/cores/cpu/blackparrot/pre-alpha-release
+	url = https://github.com/black-parrot/pre-alpha-release.git

litex/build/sim/core/Makefile

@@ -4,8 +4,9 @@ CC = gcc
 CFLAGS = -Wall -$(OPT_LEVEL) -ggdb $(if $(COVERAGE), -DVM_COVERAGE)
 LDFLAGS = -lpthread -ljson-c -lm -lstdc++ -ldl -levent
 
-CC_SRCS ?= "--cc dut.v"
-
+CC_SRCS ?= --cc dut.v
+VV_INPUT_FILE = $(if $(FILE_LIST_PATH), -f $(FILE_LIST_PATH))
+$(info $$FILE_LIST_PATH2 is [${FILE_LIST_PATH2}])
 SRC_DIR ?= .
 INC_DIR ?= .
 MOD_DIR = $(SRC_DIR)/modules
@@ -38,7 +39,8 @@ sim: mkdir $(OBJS_SIM)
 		--unroll-count 256 \
 		$(INC_DIR) \
 		-Wno-BLKANDNBLK \
-		-Wno-WIDTH
+		-Wno-WIDTH  \
+		$(VV_INPUT_FILE)
 	make -j -C $(OBJ_DIR) -f Vdut.mk Vdut
 
 .PHONY: modules

litex/soc/cores/cpu/__init__.py

@@ -32,6 +32,7 @@ class CPUNone(CPU):
 from litex.soc.cores.cpu.vexriscv import VexRiscv
 from litex.soc.cores.cpu.minerva import Minerva
 from litex.soc.cores.cpu.rocket import RocketRV64
+from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
 
 CPUS = {
     "lm32"       : LM32,
@@ -40,6 +41,7 @@ class CPUNone(CPU):
     "vexriscv"   : VexRiscv,
     "minerva"    : Minerva,
     "rocket"     : RocketRV64,
+    "blackparrot" : BlackParrotRV64,
 }
 
 # CPU Variants/Extensions Definition ---------------------------------------------------------------

litex/soc/cores/cpu/blackparrot/README

@@ -0,0 +1,7 @@
+TODO: Edit
+git submodule update --init --recursive (for blackparrot pre-alpha repo)
+cd pre_alpha_release
+follow getting_started to install blackparrot
+cd ..
+source ./setEnvironment.sh #required before running build_dut.sh
+Add $BP_TOP/external/bin to $PATH for verilator and riscv-gnu tools

litex/soc/cores/cpu/blackparrot/__init__.py

@@ -0,0 +1 @@
+from litex.soc.cores.cpu.blackparrot.core import BlackParrotRV64

litex/soc/cores/cpu/blackparrot/core.py

@@ -0,0 +1,262 @@
+# litex/soc/cores/cpu/blackparrot/core.py
+# BlackParrot Chip core support for the LiteX SoC.
+#
+# Authors: Sadullah Canakci & Cansu Demirkiran  <{scanakci,cansu}@bu.edu>
+# Copyright (c) 2019, Boston University
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+
+from migen import *
+
+from litex.soc.interconnect import axi
+from litex.soc.interconnect import wishbone
+from litex.soc.cores.cpu import CPU
+
+CPU_VARIANTS = {
+    "standard": "freechips.rocketchip.system.LitexConfig",
+#    "linux":    "freechips.rocketchip.system.LitexLinuxConfig",
+#    "full":     "freechips.rocketchip.system.LitexFullConfig",
+}
+
+GCC_FLAGS = {
+    "standard": "-march=rv64imac   -mabi=lp64 ",
+#    "linux":    "-march=rv64imac   -mabi=lp64 ",
+#    "full":     "-march=rv64imafdc -mabi=lp64 ",
+}
+
+class BlackParrotRV64(Module):
+    name                 = "blackparrot"
+    data_width           = 64
+    endianness           = "little"
+    gcc_triple           = ("riscv64-unknown-elf")
+    linker_output_format = "elf64-littleriscv"
+    io_regions           = {0x10000000: 0x70000000} # origin, length
+
+    @property
+    def mem_map(self):
+        # We do not know yet how blackparrot memory map looks like. For now, assume same as rocket.
+        return {
+            "rom"      : 0x10000000,
+            "sram"     : 0x11000000,
+            "csr"      : 0x12000000,
+            "ethmac"   : 0x30000000,
+            "main_ram" : 0x80000000,
+        }
+
+    @property
+    def gcc_flags(self):
+        flags =  "-mno-save-restore "
+        flags += GCC_FLAGS[self.variant]
+        flags += "-D__blackparrot__ "
+        return flags
+
+    def __init__(self, platform, variant="standard"):
+        assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
+        print("SC: Check how to get cpu_reset_addr properly!!!!!!!!")
+        #assert cpu_reset_addr == 0x10000000, "cpu_reset_addr hardcoded in Chisel elaboration!"
+
+        self.platform = platform
+        self.variant = variant
+        self.reset = Signal()
+
+        self.interrupt = Signal(4)
+        print(self.interrupt)
+#        self.interrupt = Signal()
+
+        self.mem_axi = mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
+        self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
+
+        self.mem_wb = mem_wb = wishbone.Interface(data_width=64, adr_width=29)
+        self.mmio_wb = mmio_wb = wishbone.Interface(data_width=64, adr_width=29)
+
+        self.interrupts = {}#TODO: Idk why this is necessary. Without this, soc_core.py raises error with no object attirubute "interrupts" 
+#        self.ibus = ibus = wishbone.Interface()
+#        self.dbus = dbus = wishbone.Interface()
+
+        self.buses     = [mem_wb, mmio_wb]
+        # # #
+
+        self.cpu_params = dict(
+            # clock, reset
+            i_clock=ClockSignal(),
+            i_reset=ResetSignal() | self.reset,
+
+            # debug (ignored)
+            #o_debug_clockeddmi_dmi_req_ready=,
+            i_debug_clockeddmi_dmi_req_valid=0,
+            i_debug_clockeddmi_dmi_req_bits_addr=0,
+            i_debug_clockeddmi_dmi_req_bits_data=0,
+            i_debug_clockeddmi_dmi_req_bits_op=0,
+            i_debug_clockeddmi_dmi_resp_ready=0,
+            #o_debug_clockeddmi_dmi_resp_valid=,
+            #o_debug_clockeddmi_dmi_resp_bits_data=,
+            #o_debug_clockeddmi_dmi_resp_bits_resp=,
+            i_debug_clockeddmi_dmiClock=0,
+            i_debug_clockeddmi_dmiReset=0,
+            #o_debug_ndreset=,
+            #o_debug_dmactive=,
+
+
+            # irq
+            i_interrupts=self.interrupt,
+
+            # axi memory (L1-cached)
+            i_mem_axi4_0_aw_ready=mem_axi.aw.ready,
+            o_mem_axi4_0_aw_valid=mem_axi.aw.valid,
+            o_mem_axi4_0_aw_bits_id=mem_axi.aw.id,
+            o_mem_axi4_0_aw_bits_addr=mem_axi.aw.addr,
+            o_mem_axi4_0_aw_bits_len=mem_axi.aw.len,
+            o_mem_axi4_0_aw_bits_size=mem_axi.aw.size,
+            o_mem_axi4_0_aw_bits_burst=mem_axi.aw.burst,
+            o_mem_axi4_0_aw_bits_lock=mem_axi.aw.lock,
+            o_mem_axi4_0_aw_bits_cache=mem_axi.aw.cache,
+            o_mem_axi4_0_aw_bits_prot=mem_axi.aw.prot,
+            o_mem_axi4_0_aw_bits_qos=mem_axi.aw.qos,
+
+            i_mem_axi4_0_w_ready=mem_axi.w.ready,
+            o_mem_axi4_0_w_valid=mem_axi.w.valid,
+            o_mem_axi4_0_w_bits_data=mem_axi.w.data,
+            o_mem_axi4_0_w_bits_strb=mem_axi.w.strb,
+            o_mem_axi4_0_w_bits_last=mem_axi.w.last,
+
+            o_mem_axi4_0_b_ready=mem_axi.b.ready,
+            i_mem_axi4_0_b_valid=mem_axi.b.valid,
+            i_mem_axi4_0_b_bits_id=mem_axi.b.id,
+            i_mem_axi4_0_b_bits_resp=mem_axi.b.resp,
+
+            i_mem_axi4_0_ar_ready=mem_axi.ar.ready,
+            o_mem_axi4_0_ar_valid=mem_axi.ar.valid,
+            o_mem_axi4_0_ar_bits_id=mem_axi.ar.id,
+            o_mem_axi4_0_ar_bits_addr=mem_axi.ar.addr,
+            o_mem_axi4_0_ar_bits_len=mem_axi.ar.len,
+            o_mem_axi4_0_ar_bits_size=mem_axi.ar.size,
+            o_mem_axi4_0_ar_bits_burst=mem_axi.ar.burst,
+            o_mem_axi4_0_ar_bits_lock=mem_axi.ar.lock,
+            o_mem_axi4_0_ar_bits_cache=mem_axi.ar.cache,
+            o_mem_axi4_0_ar_bits_prot=mem_axi.ar.prot,
+            o_mem_axi4_0_ar_bits_qos=mem_axi.ar.qos,
+
+            o_mem_axi4_0_r_ready=mem_axi.r.ready,
+            i_mem_axi4_0_r_valid=mem_axi.r.valid,
+            i_mem_axi4_0_r_bits_id=mem_axi.r.id,
+            i_mem_axi4_0_r_bits_data=mem_axi.r.data,
+            i_mem_axi4_0_r_bits_resp=mem_axi.r.resp,
+            i_mem_axi4_0_r_bits_last=mem_axi.r.last,
+
+            # axi mmio (not cached)
+            i_mmio_axi4_0_aw_ready=mmio_axi.aw.ready,
+            o_mmio_axi4_0_aw_valid=mmio_axi.aw.valid,
+            o_mmio_axi4_0_aw_bits_id=mmio_axi.aw.id,
+            o_mmio_axi4_0_aw_bits_addr=mmio_axi.aw.addr,
+            o_mmio_axi4_0_aw_bits_len=mmio_axi.aw.len,
+            o_mmio_axi4_0_aw_bits_size=mmio_axi.aw.size,
+            o_mmio_axi4_0_aw_bits_burst=mmio_axi.aw.burst,
+            o_mmio_axi4_0_aw_bits_lock=mmio_axi.aw.lock,
+            o_mmio_axi4_0_aw_bits_cache=mmio_axi.aw.cache,
+            o_mmio_axi4_0_aw_bits_prot=mmio_axi.aw.prot,
+            o_mmio_axi4_0_aw_bits_qos=mmio_axi.aw.qos,
+
+            i_mmio_axi4_0_w_ready=mmio_axi.w.ready,
+            o_mmio_axi4_0_w_valid=mmio_axi.w.valid,
+            o_mmio_axi4_0_w_bits_data=mmio_axi.w.data,
+            o_mmio_axi4_0_w_bits_strb=mmio_axi.w.strb,
+            o_mmio_axi4_0_w_bits_last=mmio_axi.w.last,
+
+            o_mmio_axi4_0_b_ready=mmio_axi.b.ready,
+            i_mmio_axi4_0_b_valid=mmio_axi.b.valid,
+            i_mmio_axi4_0_b_bits_id=mmio_axi.b.id,
+            i_mmio_axi4_0_b_bits_resp=mmio_axi.b.resp,
+
+            i_mmio_axi4_0_ar_ready=mmio_axi.ar.ready,
+            o_mmio_axi4_0_ar_valid=mmio_axi.ar.valid,
+            o_mmio_axi4_0_ar_bits_id=mmio_axi.ar.id,
+            o_mmio_axi4_0_ar_bits_addr=mmio_axi.ar.addr,
+            o_mmio_axi4_0_ar_bits_len=mmio_axi.ar.len,
+            o_mmio_axi4_0_ar_bits_size=mmio_axi.ar.size,
+            o_mmio_axi4_0_ar_bits_burst=mmio_axi.ar.burst,
+            o_mmio_axi4_0_ar_bits_lock=mmio_axi.ar.lock,
+            o_mmio_axi4_0_ar_bits_cache=mmio_axi.ar.cache,
+            o_mmio_axi4_0_ar_bits_prot=mmio_axi.ar.prot,
+            o_mmio_axi4_0_ar_bits_qos=mmio_axi.ar.qos,
+
+            o_mmio_axi4_0_r_ready=mmio_axi.r.ready,
+            i_mmio_axi4_0_r_valid=mmio_axi.r.valid,
+            i_mmio_axi4_0_r_bits_id=mmio_axi.r.id,
+            i_mmio_axi4_0_r_bits_data=mmio_axi.r.data,
+            i_mmio_axi4_0_r_bits_resp=mmio_axi.r.resp,
+            i_mmio_axi4_0_r_bits_last=mmio_axi.r.last,
+        )
+
+        # adapt axi interfaces to wishbone
+        mem_a2w = ResetInserter()(
+            axi.AXI2Wishbone(mem_axi, mem_wb, base_address=0))
+        mmio_a2w = ResetInserter()(
+            axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
+        # NOTE: AXI2Wishbone FSMs must be reset with the CPU!
+        self.comb += [
+            mem_a2w.reset.eq(ResetSignal() | self.reset),
+            mmio_a2w.reset.eq(ResetSignal() | self.reset),
+        ]
+
+        # down-convert wishbone from 64 to 32 bit data width
+        #NOTE: Recent Rocket core.py does not have this interface!!!
+#        mem_dc = wishbone.Converter(mem_wb, ibus)
+#        mmio_dc = wishbone.Converter(mmio_wb, dbus)
+
+   #     self.submodules += mem_a2w, mem_dc, mmio_a2w, mmio_dc #need to change most probably!
+        self.submodules += mem_a2w,  mmio_a2w 
+         #need to change most probably!
+
+        # add verilog sources
+        self.add_sources(platform, variant)
+        print("DEBUG")
+
+
+    def set_reset_address(self, reset_address):#note sure if reset address needs to be changed for BB
+        assert not hasattr(self, "reset_address")
+        self.reset_address = reset_address
+        assert reset_address == 0x10000000, "cpu_reset_addr hardcoded in during elaboration!"
+
+
+    @staticmethod
+    def add_sources(platform, variant="standard"):
+        #This function should be updated. A new platform specific function that accepts a command similar to -f in verilator will be perfect!
+        vdir = os.path.join(
+            os.path.abspath(os.path.dirname(__file__)),"pre-alpha-release", "verilog",variant)
+        incdir = os.path.join(
+            os.path.abspath(os.path.dirname(__file__)),"pre-alpha-release", "verilog",variant)
+        print("Adding the sources")
+        vdir = os.path.join(
+                os.path.abspath(os.path.dirname(__file__)),"verilog")
+        platform.add_source_dir(vdir)
+
+    def do_finalize(self):
+        assert hasattr(self, "reset_address")
+        self.specials += Instance("ExampleBlackparrotSystem", **self.cpu_params)
+
+