core/Trigger: also apply mask to trigger value (avoid having doing it…

… in software).
enjoy-digital · Sep 2, 2020 · 219a901 · 219a901
1 parent 12be703
commit 219a901
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Showing 2 changed files with 2 additions and 3 deletions.
diff --git a/litescope/core.py b/litescope/core.py
@@ -80,7 +80,7 @@ def __init__(self, data_width, depth=16):
         self.submodules += flush
         self.comb += [
             flush.wait.eq(~(~enable & enable_d)), # flush when disabling
-            hit.eq((sink.data & mem.source.mask) == mem.source.value),
+            hit.eq((sink.data & mem.source.mask) == (mem.source.value & mem.source.mask)),
             mem.source.ready.eq((enable & hit) | ~flush.done),
         ]
 
@@ -92,7 +92,6 @@ def __init__(self, data_width, depth=16):
             source.hit.eq(done)
         ]
 
-
 class _SubSampler(Module, AutoCSR):
     def __init__(self, data_width):
         self.sink   = sink   = stream.Endpoint(core_layout(data_width))

diff --git a/litescope/software/driver/analyzer.py b/litescope/software/driver/analyzer.py
@@ -80,7 +80,7 @@ def add_trigger(self, value=0, mask=0, cond=None):
         if cond is not None:
             for k, v in cond.items():
                 value |= getattr(self, k + "_o")*v
-                mask |= getattr(self, k + "_m")
+                mask  |= getattr(self, k + "_m")
         self.trigger_mem_mask.write(mask)
         self.trigger_mem_value.write(value)
         self.trigger_mem_write.write(1)