litedram_gen: add initial Ultrascale+ support with XCU1525 .yml example.

examples/xcu1525.yml

@@ -0,0 +1,51 @@
+#
+# This file is part of LiteDRAM.
+#
+# Copyright (c) 2021 Florent Kermarrec <[email protected]>
+# SPDX-License-Identifier: BSD-2-Clause
+
+{
+    # General ------------------------------------------------------------------
+    "cpu":        "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
+    "speedgrade": -2,         # FPGA speedgrade
+    "memtype":    "DDR4",     # DRAM type
+
+    # PHY ----------------------------------------------------------------------
+    "cmd_latency":     1,            # Command additional latency
+    "sdram_module":    "MT40A512M8", # SDRAM modules of the board or SO-DIMM
+    "sdram_module_nb": 8,            # Number of byte groups
+    "sdram_rank_nb":   1,            # Number of ranks
+    "sdram_phy":       "USPDDRPHY",  # Type of FPGA PHY
+
+    # Electrical ---------------------------------------------------------------
+    "rtt_nom": "40ohm", # Nominal termination
+    "rtt_wr":  "120ohm", # Write termination
+    "ron":     "34ohm", # Output driver impedance
+
+    # Frequency ----------------------------------------------------------------
+    "input_clk_freq":   150e6, # Input clock frequency
+    "sys_clk_freq":     150e6, # System clock frequency (DDR_clk = 4 x sys_clk)
+    "iodelay_clk_freq": 300e6, # IODELAYs reference clock frequency
+
+    # Core ---------------------------------------------------------------------
+    "cmd_buffer_depth": 16,    # Depth of the command buffer
+
+    # User Ports ---------------------------------------------------------------
+    "user_ports": {
+        "axi_0" : {
+            "type": "axi",
+            "id_width": 32,
+        },
+        "wishbone_0" : {
+            "type": "wishbone",
+        },
+        "native_0" : {
+            "type": "native",
+        },
+        "fifo_0" : {
+            "type":  "fifo",
+            "base":  0x00000000,
+            "depth": 0x01000000,
+        },
+    },
+}

litedram/gen.py

@@ -364,6 +364,45 @@ def __init__(self, platform, core_config):
         # IODelay Ctrl
         self.submodules.idelayctrl = USIDELAYCTRL(self.cd_iodelay, cd_sys=self.cd_sys)
 
+class LiteDRAMUSPDDRPHYCRG(Module):
+    def __init__(self, platform, core_config):
+        assert core_config["memtype"] in ["DDR4"]
+        self.clock_domains.cd_por       = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys       = ClockDomain()
+        self.clock_domains.cd_sys4x     = ClockDomain()
+        self.clock_domains.cd_sys4x_pll = ClockDomain()
+        self.clock_domains.cd_iodelay   = ClockDomain()
+
+        # # #
+
+        clk = platform.request("clk")
+        rst = platform.request("rst")
+
+        # Power On Reset
+        por_count = Signal(32, reset=int(core_config["input_clk_freq"]*100/1e3)) # 100ms
+        por_done  = Signal()
+        self.comb += self.cd_por.clk.eq(clk)
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+
+        # Sys PLL
+        self.submodules.sys_pll = sys_pll = USPMMCM(speedgrade=core_config["speedgrade"])
+        self.comb += sys_pll.reset.eq(rst)
+        sys_pll.register_clkin(clk, core_config["input_clk_freq"])
+        sys_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
+        sys_pll.create_clkout(self.cd_sys4x_pll, 4*core_config["sys_clk_freq"], buf=None)
+        self.comb += platform.request("pll_locked").eq(sys_pll.locked)
+        self.specials += [
+            Instance("BUFGCE_DIV", name="main_bufgce_div",
+                p_BUFGCE_DIVIDE=4,
+                i_CE=por_done, i_I=self.cd_sys4x_pll.clk, o_O=self.cd_sys.clk),
+            Instance("BUFGCE", name="main_bufgce",
+                i_CE=por_done, i_I=self.cd_sys4x_pll.clk, o_O=self.cd_sys4x.clk),
+        ]
+
+        # IODelay Ctrl
+        self.submodules.idelayctrl = USPIDELAYCTRL(self.cd_iodelay, cd_sys=self.cd_sys)
+
 # LiteDRAMCoreControl ------------------------------------------------------------------------------
 
 class LiteDRAMCoreControl(Module, AutoCSR):
@@ -403,8 +442,10 @@ def __init__(self, platform, core_config, **kwargs):
             self.submodules.crg = crg = LiteDRAMECP5DDRPHYCRG(platform, core_config)
         elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
             self.submodules.crg = LiteDRAMS7DDRPHYCRG(platform, core_config)
-        elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY]:
+        elif core_config["sdram_phy"] in [litedram_phys.USDDRPHY]:
             self.submodules.crg = LiteDRAMUSDDRPHYCRG(platform, core_config)
+        elif core_config["sdram_phy"] in [litedram_phys.USPDDRPHY]:
+            self.submodules.crg = LiteDRAMUSPDDRPHYCRG(platform, core_config)
 
         # DRAM -------------------------------------------------------------------------------------
         platform.add_extension(get_dram_ios(core_config))