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Refactoring & cleanup of linkage properties #5836

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6c20dea
RISC-V: refactor `initRVRealRegisterLinkage()` to use (new) FOR_EACH_…
janvrany Nov 29, 2020
93a8fa6
RISC-V: move FOR_EACH_*_REGISTER() macros to OMRLinkage.hpp
janvrany Dec 2, 2020
52d024d
RISC-V: implement ++ operators for TR::RealRegister::RegNum
janvrany Feb 12, 2021
e6bd416
RISC-V: introduce RVLinkageProperties::initialize() to initialize der…
janvrany Feb 12, 2021
b7285f1
RISC-V: move initialization of (system) linkage properties to its own…
janvrany Feb 15, 2021
bb749d8
RISC-V: make system linkage properties static
janvrany Feb 15, 2021
1789e59
RISC-V: rename RV_Reserved register flag to Reserved
janvrany Feb 16, 2021
b75af37
CMake: add toolchain file for PPC64 for cross-compilation
janvrany Feb 19, 2021
ddda7a9
CMake: add toolchain file for PPC64LE for cross-compilation
janvrany Mar 2, 2021
234df9a
POWER: reorder PPCLinkageProperties so that common members are first
janvrany Feb 22, 2021
7f8da62
POWER: rename PPC_Reserved register flag to Reserved
janvrany Feb 22, 2021
a4318ab
Common ++ operators for RegNum type
janvrany Feb 26, 2021
5fbeb36
RISC-V: remove unnecessary RealRegister.hpp
janvrany Feb 26, 2021
fe7bcab
POWER: remove unused _alternateStackPointerRegister from linkage prop…
janvrany Feb 26, 2021
10e5c9b
POWER: Use OMRCodeGenerator::getStackPointerRegister() when possible
janvrany Feb 26, 2021
05f7605
POWER: rename _normalStackPointerRegister to just _stackPointerRegister
janvrany Feb 26, 2021
c1c338f
POWER: minor readability improvement in linkage members
janvrany Mar 3, 2021
6c25811
POWER: add TODO comments on some linkage properties members
janvrany Mar 3, 2021
08534c2
POWER: introduce PPCLinkageProperties::initialize() to initialize der…
janvrany Mar 3, 2021
3376c96
Common parts new common base class OMR::LinkageProperties
janvrany Mar 4, 2021
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POWER: reorder PPCLinkageProperties so that common members are first
This is a preparation for commoning.

Signed-off-by: Jan Vrany <[email protected]>
janvrany committed Mar 3, 2021

Verified

This commit was signed with the committer’s verified signature.
commit 234df9a56f65c4691fc438e29506f45388e3ae44
116 changes: 60 additions & 56 deletions compiler/p/codegen/OMRLinkage.hpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
@@ -92,29 +92,13 @@ struct PPCLinkageProperties
uint8_t _firstIntegerArgumentRegister;
uint8_t _numFloatArgumentRegisters;
uint8_t _firstFloatArgumentRegister;
uint8_t _numVectorArgumentRegisters;
uint8_t _firstVectorArgumentRegister;
TR::RealRegister::RegNum _argumentRegisters[TR::RealRegister::NumRegisters];
uint8_t _firstIntegerReturnRegister;
uint8_t _firstFloatReturnRegister;
uint8_t _firstVectorReturnRegister;
TR::RealRegister::RegNum _returnRegisters[TR::RealRegister::NumRegisters];
uint8_t _numAllocatableIntegerRegisters;
uint8_t _firstAllocatableIntegerArgumentRegister;
uint8_t _lastAllocatableIntegerVolatileRegister;
uint8_t _numAllocatableFloatRegisters;
uint8_t _firstAllocatableFloatArgumentRegister;
uint8_t _lastAllocatableFloatVolatileRegister;
uint8_t _numAllocatableVectorRegisters;
uint8_t _firstAllocatableVectorArgumentRegister;
uint8_t _lastAllocatableVectortVolatileRegister;
uint8_t _numAllocatableCCRegisters;
uint32_t _allocationOrder[TR::RealRegister::NumRegisters];
uint32_t _preservedRegisterMapForGC;
TR::RealRegister::RegNum _methodMetaDataRegister;
TR::RealRegister::RegNum _normalStackPointerRegister;
TR::RealRegister::RegNum _alternateStackPointerRegister;
TR::RealRegister::RegNum _TOCBaseRegister;
TR::RealRegister::RegNum _computedCallTargetRegister; // for icallVMprJavaSendPatchupVirtual
TR::RealRegister::RegNum _vtableIndexArgumentRegister; // for icallVMprJavaSendPatchupVirtual
TR::RealRegister::RegNum _j9methodArgumentRegister; // for icallVMprJavaSendStatic
@@ -125,8 +109,6 @@ struct PPCLinkageProperties

uint32_t getNumFloatArgRegs() const {return _numFloatArgumentRegisters;}

uint32_t getNumVectorArgRegs() const {return _numVectorArgumentRegisters;}

uint32_t getProperties() const {return _properties;}

uint32_t getCallerCleanup() const {return (_properties & CallerCleanup);}
@@ -139,8 +121,6 @@ struct PPCLinkageProperties

uint32_t getFloatsInRegisters() const {return (_properties & FloatsInRegisters);}

uint32_t getSmallIntParmsAlignedRight() const { return (_properties & SmallIntParmsAlignedRight); }

uint32_t getRegisterFlags(TR::RealRegister::RegNum regNum) const
{
return _registerFlags[regNum];
@@ -151,11 +131,6 @@ struct PPCLinkageProperties
return (_registerFlags[regNum] & Preserved);
}

uint32_t getReserved(TR::RealRegister::RegNum regNum) const
{
return (_registerFlags[regNum] & PPC_Reserved);
}

uint32_t getIntegerReturn(TR::RealRegister::RegNum regNum) const
{
return (_registerFlags[regNum] & IntegerReturn);
@@ -198,12 +173,6 @@ struct PPCLinkageProperties
return _argumentRegisters[_firstFloatArgumentRegister+index];
}

// get the indexth vector argument register
TR::RealRegister::RegNum getVectorArgumentRegister(uint32_t index) const
{
return _argumentRegisters[_firstVectorArgumentRegister+index];
}

// get the indexth integer return register
TR::RealRegister::RegNum getIntegerReturnRegister(uint32_t index) const
{
@@ -216,12 +185,6 @@ struct PPCLinkageProperties
return _returnRegisters[_firstFloatReturnRegister+index];
}

// get the indexth vector return register
TR::RealRegister::RegNum getVectorReturnRegister(uint32_t index) const
{
return _returnRegisters[_firstVectorReturnRegister+index];
}

TR::RealRegister::RegNum getArgument(uint32_t index) const
{
return _argumentRegisters[index];
@@ -234,7 +197,7 @@ struct PPCLinkageProperties

TR::RealRegister::RegNum getIntegerReturnRegister() const
{
return _returnRegisters[0];
return _returnRegisters[_firstIntegerReturnRegister];
}

// for 32-bit use only
@@ -252,7 +215,7 @@ struct PPCLinkageProperties
// for 64-bit use only
TR::RealRegister::RegNum getLongReturnRegister() const
{
return _returnRegisters[0];
return _returnRegisters[_firstIntegerReturnRegister];
}

TR::RealRegister::RegNum getFloatReturnRegister() const
@@ -265,26 +228,11 @@ struct PPCLinkageProperties
return _returnRegisters[_firstFloatReturnRegister];
}

TR::RealRegister::RegNum getVectorReturnRegister() const
{
return _returnRegisters[_firstVectorReturnRegister];
}

int32_t getNumAllocatableIntegerRegisters() const
{
return _numAllocatableIntegerRegisters;
}

int32_t getFirstAllocatableIntegerArgumentRegister() const
{
return _firstAllocatableIntegerArgumentRegister;
}

int32_t getLastAllocatableIntegerVolatileRegister() const
{
return _lastAllocatableIntegerVolatileRegister;
}

int32_t getNumAllocatableFloatRegisters() const
{
return _numAllocatableFloatRegisters;
@@ -351,9 +299,65 @@ struct PPCLinkageProperties
int32_t getOffsetToFirstLocal() const {return _offsetToFirstLocal;}

uint32_t getNumberOfDependencyGPRegisters() const {return _numberOfDependencyGPRegisters;}

// POWER specific properties follows
uint8_t _numVectorArgumentRegisters;
uint8_t _firstVectorArgumentRegister;
uint8_t _firstVectorReturnRegister;
uint8_t _firstAllocatableIntegerArgumentRegister;
uint8_t _lastAllocatableIntegerVolatileRegister;
uint8_t _firstAllocatableFloatArgumentRegister;
uint8_t _lastAllocatableFloatVolatileRegister;
uint8_t _numAllocatableVectorRegisters;
uint8_t _firstAllocatableVectorArgumentRegister;
uint8_t _lastAllocatableVectortVolatileRegister;
uint8_t _numAllocatableCCRegisters;
uint32_t _allocationOrder[TR::RealRegister::NumRegisters];
uint32_t _preservedRegisterMapForGC;

TR::RealRegister::RegNum _normalStackPointerRegister;
TR::RealRegister::RegNum _alternateStackPointerRegister;
TR::RealRegister::RegNum _TOCBaseRegister;

uint32_t getNumVectorArgRegs() const {return _numVectorArgumentRegisters;}

uint32_t getSmallIntParmsAlignedRight() const { return (_properties & SmallIntParmsAlignedRight); }

uint32_t getReserved(TR::RealRegister::RegNum regNum) const
{
return (_registerFlags[regNum] & PPC_Reserved);
}

// get the indexth vector argument register
TR::RealRegister::RegNum getVectorArgumentRegister(uint32_t index) const
{
return _argumentRegisters[_firstVectorArgumentRegister+index];
}

// get the indexth vector return register
TR::RealRegister::RegNum getVectorReturnRegister(uint32_t index) const
{
return _returnRegisters[_firstVectorReturnRegister+index];
}

TR::RealRegister::RegNum getVectorReturnRegister() const
{
return _returnRegisters[_firstVectorReturnRegister];
}

int32_t getFirstAllocatableIntegerArgumentRegister() const
{
return _firstAllocatableIntegerArgumentRegister;
}

int32_t getLastAllocatableIntegerVolatileRegister() const
{
return _lastAllocatableIntegerVolatileRegister;
}

};

}
} // namespace TR

namespace OMR
{
13 changes: 13 additions & 0 deletions compiler/riscv/codegen/OMRLinkage.hpp
Original file line number Diff line number Diff line change
@@ -230,6 +230,19 @@ struct RVLinkageProperties
return _returnRegisters[_firstIntegerReturnRegister];
}

// for 32-bit use only
TR::RealRegister::RegNum getLongLowReturnRegister() const
{
return _returnRegisters[1];
}

// for 32-bit use only
TR::RealRegister::RegNum getLongHighReturnRegister() const
{
return _returnRegisters[0];
}

// for 64-bit use only
TR::RealRegister::RegNum getLongReturnRegister() const
{
return _returnRegisters[_firstIntegerReturnRegister];