1.1.0

Allow byte access for Avalon, AXI and Wishbone

1.0.0

With 1.0.0 we includes all planned commands.
See therefore the Readme.

Unit tests

The release includes for all commands some Unittests for GHDL and Modelsim/Questa

0.1.0

SimStm

Included commands:

• basics
• Operations (except the future ones)
• Signals
• Bus
• Array
• and others

Missing commands:

• all file types

Bus

Basic bus masters for Avalon Memory Mapped, Axi 4 Lite and Wishbone are included.

State

SimStm can be used in production for HDL simulation tests.