drivers: i2c: i2c_ll_stm32_v1

In rare cases, the I2C driver runs the N==2 logic for I2C receives when N>2. This change breaks early when handling the last 2 bytes for transactions with N>2 Signed-off-by: Mikhail Skobov <[email protected]>
e-rk · May 3, 2024 · 7d362e0 · 7d362e0
1 parent 5d44ebf
commit 7d362e0
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/drivers/i2c/i2c_ll_stm32_v1.c b/drivers/i2c/i2c_ll_stm32_v1.c
@@ -359,6 +359,14 @@ static inline void handle_rxne(const struct device *dev)
 			k_sem_give(&data->device_sync_sem);
 			break;
 		case 2:
+			/*
+			 * 2-byte reception for N > 3 has already set the NACK
+			 * bit, and must not set the POS bit. See pg. 854 in
+			 * the F4 reference manual (RM0090).
+			 */
+			if (data->current.msg->len > 2) {
+				break;
+			}
 			LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
 			LL_I2C_EnableBitPOS(i2c);
 			__fallthrough;