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JIT: Added SVE_GK_2A and SVE_GL_1A arm64 encodings #95707

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merged 5 commits into from
Dec 8, 2023
Merged

JIT: Added SVE_GK_2A and SVE_GL_1A arm64 encodings #95707

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2173f7d
Added SVE_GK_2A and SVE_GL_1A arm64 encodings
TIHan Dec 6, 2023
5b26c63
Use SCALABLE_S for sm4e
TIHan Dec 6, 2023
7d64a67
Formatting
TIHan Dec 6, 2023
815257d
Removing `insOpts opt` from emitIns_R
TIHan Dec 7, 2023
d23b3ce
Merge branch 'main' into SVE_GK_2A
TIHan Dec 7, 2023
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12 changes: 12 additions & 0 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10533,6 +10533,18 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R_I(INS_sve_uqrshrn, EA_SCALABLE, REG_V15, REG_V12, 1,
INS_OPTS_SCALABLE_H); // UQRSHRN <Zd>.H, {<Zn1>.S-<Zn2>.S }, #<const>

// IF_SVE_GK_2A
theEmitter->emitIns_R_R(INS_sve_aesd, EA_SCALABLE, REG_V0, REG_V0, INS_OPTS_SCALABLE_B); // AESD <Zdn>.B,
// <Zdn>.B, <Zm>.B
theEmitter->emitIns_R_R(INS_sve_aese, EA_SCALABLE, REG_V1, REG_V2, INS_OPTS_SCALABLE_B); // AESE <Zdn>.B,
// <Zdn>.B, <Zm>.B
theEmitter->emitIns_R_R(INS_sve_sm4e, EA_SCALABLE, REG_V3, REG_V5, INS_OPTS_SCALABLE_S); // SM4E <Zdn>.S,
// <Zdn>.S, <Zm>.S

// IF_SVE_GL_1A
theEmitter->emitIns_R(INS_sve_aesimc, EA_SCALABLE, REG_V0, INS_OPTS_SCALABLE_B); // AESIMC <Zdn>.B, <Zdn>.B
theEmitter->emitIns_R(INS_sve_aesmc, EA_SCALABLE, REG_V5, INS_OPTS_SCALABLE_B); // AESMC <Zdn>.B, <Zdn>.B

#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
Expand Down
98 changes: 97 additions & 1 deletion src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1124,6 +1124,31 @@ void emitter::emitInsSanityCheck(instrDesc* id)
assert(id->idInsOpt() == INS_OPTS_SCALABLE_H);
break;

case IF_SVE_GK_2A: // ................ ......mmmmmddddd -- SVE2 crypto destructive binary operations
elemsize = id->idOpSize();
assert(insOptsScalable(id->idInsOpt()));
assert(isVectorRegister(id->idReg1())); // ddddd
assert(isVectorRegister(id->idReg2())); // mmmmm
#ifdef DEBUG
if (id->idInsOpt() == INS_OPTS_SCALABLE_S)
{
assert(id->idIns() == INS_sve_sm4e);
}
else
{
assert(id->idInsOpt() == INS_OPTS_SCALABLE_B);
}
#endif // DEBUG
assert(isScalableVectorSize(elemsize));
break;

case IF_SVE_GL_1A: // ................ ...........ddddd -- SVE2 crypto unary operations
elemsize = id->idOpSize();
assert(insOptsScalable(id->idInsOpt()));
assert(isVectorRegister(id->idReg1())); // ddddd
assert(isScalableVectorSize(elemsize));
break;

default:
printf("unexpected format %s\n", emitIfName(id->idInsFmt()));
assert(!"Unexpected format");
Expand Down Expand Up @@ -5468,7 +5493,7 @@ void emitter::emitIns_I(instruction ins, emitAttr attr, ssize_t imm)
* Add an instruction referencing a single register.
*/

void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg)
void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg, insOpts opt /* = INS_OPTS_NONE */)
{
insFormat fmt = IF_NONE;
instrDesc* id = nullptr;
Expand All @@ -5478,13 +5503,15 @@ void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg)
{
case INS_br:
case INS_ret:
assert(opt == INS_OPTS_NONE);
assert(isGeneralRegister(reg));
id = emitNewInstrSmall(attr);
id->idReg1(reg);
fmt = IF_BR_1A;
break;

case INS_dczva:
assert(opt == INS_OPTS_NONE);
assert(isGeneralRegister(reg));
assert(attr == EA_8BYTE);
id = emitNewInstrSmall(attr);
Expand All @@ -5493,11 +5520,24 @@ void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg)
break;

case INS_mrs_tpid0:
assert(opt == INS_OPTS_NONE);
id = emitNewInstrSmall(attr);
id->idReg1(reg);
fmt = IF_SR_1A;
break;

case INS_sve_aesmc:
case INS_sve_aesimc:
assert(opt == INS_OPTS_SCALABLE_B);
id = emitNewInstrSmall(attr);
id->idInsOpt(opt);
id->idReg1(reg);
assert(insOptsScalable(id->idInsOpt()));
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assert(isVectorRegister(reg)); // ddddd
assert(isScalableVectorSize(attr));
fmt = IF_SVE_GL_1A;
break;

default:
unreached();
}
Expand Down Expand Up @@ -6688,6 +6728,25 @@ void emitter::emitIns_R_R(
}
break;

case INS_sve_aese:
case INS_sve_aesd:
case INS_sve_sm4e:
assert(insOptsScalable(opt));
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
#ifdef DEBUG
if (opt == INS_OPTS_SCALABLE_S)
{
assert(ins == INS_sve_sm4e);
}
else
{
assert(opt == INS_OPTS_SCALABLE_B);
}
#endif // DEBUG
fmt = IF_SVE_GK_2A;
break;

default:
unreached();
break;
Expand Down Expand Up @@ -14355,6 +14414,19 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
dst += emitOutput_Instr(dst, code);
break;

case IF_SVE_GK_2A: // ................ ......mmmmmddddd -- SVE2 crypto destructive binary operations
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
code |= insEncodeReg_V_9_to_5(id->idReg2()); // mmmmm
dst += emitOutput_Instr(dst, code);
break;

case IF_SVE_GL_1A: // ................ ...........ddddd -- SVE2 crypto unary operations
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
dst += emitOutput_Instr(dst, code);
break;

default:
assert(!"Unexpected format");
break;
Expand Down Expand Up @@ -16695,6 +16767,20 @@ void emitter::emitDispInsHelp(
emitDispImm(emitGetInsSC(id), false); // iiii
break;

// <Zdn>.B, <Zdn>.B, <Zm>.B
// <Zdn>.S, <Zdn>.S, <Zm>.S
case IF_SVE_GK_2A: // ................ ......mmmmmddddd -- SVE2 crypto destructive binary operations
emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd
emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd
emitDispSveReg(id->idReg2(), id->idInsOpt(), false); // mmmmm
break;

// <Zdn>.B, <Zdn>.B
case IF_SVE_GL_1A: // ................ ...........ddddd -- SVE2 crypto unary operations
emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd
emitDispSveReg(id->idReg1(), id->idInsOpt(), false); // ddddd
break;

default:
printf("unexpected format %s", emitIfName(id->idInsFmt()));
assert(!"unexpectedFormat");
Expand Down Expand Up @@ -19121,6 +19207,16 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
}
break;

case IF_SVE_GK_2A: // ................ ......mmmmmddddd -- SVE2 crypto destructive binary operations
result.insThroughput = PERFSCORE_THROUGHPUT_2C;
result.insLatency = PERFSCORE_LATENCY_2C;
break;

case IF_SVE_GL_1A: // ................ ...........ddddd -- SVE2 crypto unary operations
result.insThroughput = PERFSCORE_THROUGHPUT_2C;
result.insLatency = PERFSCORE_LATENCY_2C;
break;

default:
// all other instructions
perfScoreUnhandledInstruction(id, &result);
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/emitarm64.h
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Expand Up @@ -963,7 +963,7 @@ void emitIns(instruction ins);

void emitIns_I(instruction ins, emitAttr attr, ssize_t imm);

void emitIns_R(instruction ins, emitAttr attr, regNumber reg);
void emitIns_R(instruction ins, emitAttr attr, regNumber reg, insOpts opt = INS_OPTS_NONE);
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void emitIns_R_I(instruction ins,
emitAttr attr,
Expand Down
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