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Ensure that GT_CNS_VEC is handled in LinearScan::isMatchingConstant #70171

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merged 3 commits into from
Jun 3, 2022
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Ensure that GT_CNS_VEC is handled in LinearScan::isMatchingConstant #70171

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76c0d07
Ensure that GT_CNS_VEC is handled in LinearScan::isMatchingConstant
tannergooding Jun 2, 2022
fe98a78
Ensure an Arm64 assert includes GT_CNS_VEC
tannergooding Jun 2, 2022
0e08fd7
Update src/coreclr/jit/codegenarmarch.cpp
tannergooding Jun 2, 2022
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2 changes: 1 addition & 1 deletion src/coreclr/jit/codegenarmarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -144,7 +144,7 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
if (treeNode->IsReuseRegVal())
{
// For now, this is only used for constant nodes.
assert((treeNode->OperGet() == GT_CNS_INT) || (treeNode->OperGet() == GT_CNS_DBL));
assert((treeNode->OperGet() == GT_CNS_INT) || (treeNode->OperGet() == GT_CNS_DBL) || (treeNode->OperGet() == GT_CNS_VEC));
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JITDUMP(" TreeNode is marked ReuseReg\n");
return;
}
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7 changes: 7 additions & 0 deletions src/coreclr/jit/lsra.cpp
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Expand Up @@ -2695,6 +2695,7 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo
}
break;
}

case GT_CNS_DBL:
{
// For floating point constants, the values must be identical, not simply compare
Expand All @@ -2706,6 +2707,12 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo
}
break;
}

case GT_CNS_VEC:
{
return GenTreeVecCon::Equals(refPosition->treeNode->AsVecCon(), otherTreeNode->AsVecCon());
}

default:
break;
}
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1 change: 1 addition & 0 deletions src/coreclr/jit/lsraxarch.cpp
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Expand Up @@ -147,6 +147,7 @@ int LinearScan::BuildNode(GenTree* tree)
case GT_CNS_INT:
case GT_CNS_LNG:
case GT_CNS_DBL:
case GT_CNS_VEC:
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Noting ARM64 already had a path here since it needed special handling for Zero and AllBitsSet, it just wasn't getting used in LSRA

{
srcCount = 0;
assert(dstCount == 1);
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