[Mono] Add SIMD intrinsics for Vector64/128 "All" and "Any" variants of GT/GE/LT/LE #65889
Conversation
simonrozsival
requested review from
vargaz,
lambdageek,
SamMonoRT and
imhameed
as code owners
ghost
assigned 
…intrinsics-gt-lt-all-any
…intrinsics-gt-lt-all-any
| @@ -7736,6 +7736,10 @@ process_bb (EmitContext *ctx, MonoBasicBlock *bb) | |||
| values [ins->dreg] = LLVMConstNull (type_to_llvm_type (ctx, m_class_get_byval_arg (ins->klass))); | |||
| break; | |||
| } | |||
| case OP_XONES: { | |||
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nit: XONES is a confusing term
This means AllBitsSet where-as many users may interpret it as the integer 1.
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OP_XONES is already in the repo, it just hasn't been implemented in mini-llvm so far
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Sure, I still felt it was important to call out. This is a generally confusing term and it might be worth considering doing a rename to avoid the confusion.
We explicitly avoided the term ones for the managed side in API review because it is people read it and think it refers to Create(1) (broadcast 1 to all elements) or Create(1, 1, ..., 1) (explicitly set each element to 1).
Where-as it actually produces something that is akin to the bitwise pattern ~0.
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I see. Thanks for the explanation and context.
…sival/runtime into vector-intrinsics-gt-lt-all-any
…intrinsics-gt-lt-all-any
…intrinsics-gt-lt-all-any
Related to #64072
GreaterThanAllGreaterThanAnyGreaterThanOrEqualAllGreaterThanOrEqualAnyLessThanAllLessThanAnyLessThanOrEqualAllLessThanOrEqualAny