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Revert potential UB due to aliasing + more WB removals #111733
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
Some regressions with barrier-free code e.g. https://www.diffchecker.com/Sz7TI32G/ (when we save a nonbyref-like struct with gc pointers to a field of byreflike struct) |
addr = m_store->AsIndir()->Addr(); | ||
indirFlags = m_store->gtFlags & GTF_IND_COPYABLE_FLAGS; | ||
indirFlags = m_store->gtFlags & flagsToPropagate; |
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Is there any benefit to adding something like
if (m_store->AsBlk()->GetLayout()->IsStackOnly())
indirFlags |= GTF_IND_TGT_NOT_HEAP;
here (and in morphblock.cpp)? Or will m_store
already have this flag set for this case?
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@jakobbotsch I don't see diffs, but this PR already produces too many missing contexts 🙂
Presumably, this is not enough, because some GT_STORE_BLK have this flag without its layout being IsStackOnly. E.g. when we store a non-byreflike struct to byreflike-struct's field
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Yeah, it makes sense to me to propagate the flags, but it also makes sense to me to set the flags anew here, since the decomposition is "losing" the information at this point. I will leave it up to you.
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Added. Looks like MihuBot found a few diffs with it
PTAL @jakobbotsch Diffs: MihuBot/runtime-utils#932 (SPMI diffs report missing contexts: https://dev.azure.com/dnceng-public/public/_build/results?buildId=926588&view=ms.vss-build-web.run-extensions-tab) There are a few regressions where WB is lighter than no-WB (e.g. https://www.diffchecker.com/Sz7TI32G/) [InlineArray(4)]
internal struct ArgumentData<T>
{
private T _arg0;
}
[StructLayout(LayoutKind.Sequential)]
internal ref struct Test
{
[MethodImpl(MethodImplOptions.NoInlining)]
public Test(object a)
{
_args[1] = a;
}
internal ArgumentData<object?> _args;
} here we end up with:
and we can't extract class info easily (stind.ref opcode doesn't contain any class token nor we can extract it from ops). I might look into this and more cases separately (overall it's a regression only for previously merged PR) |
* main: (22 commits) Clean up Stopwatch a bit (dotnet#111834) JIT: Fix embedded broadcast simd size (dotnet#111638) Revert potential UB due to aliasing + more WB removals (dotnet#111733) re-enable acceleration of Vector512<long>.op_Multiply (dotnet#111832) Handle OSSL 3.4 change to SAN:othername formatting JIT: Fix stack allocated arrays for NativeAOT (dotnet#111827) JIT: enhance RBO inference for similar compares to constants (dotnet#111766) JIT: Don't run optSetBlockWeights when we have PGO data (dotnet#111764) [Android] Make sure RuntimeFlavor=CoreCLR when clr subset is specified (dotnet#111821) Change empty subject test certificate to include a critical SAN. Fix reversed code offsets in GcInfo (dotnet#111792) Swap some libraries areas between leads (dotnet#111816) Add left-handed spherical and cylindrical billboards (dotnet#109605) JIT: revise `optRelopImpliesRelop` to always set `reverseSense` (dotnet#111803) Fix Zip64ExtraField handling (dotnet#111802) Add build support for Android+CoreCLR (dotnet#110471) arm64: Add bic(s) compact encoding (dotnet#111452) JIT: Ensure `BBF_PROF_WEIGHT` flag is set when we have PGO data (dotnet#111780) Add support for AVX10.2, Add AVX10.2 API surface and template tests (dotnet#111209) JIT: Preliminary for enabling inlining late devirted calls (dotnet#111782) ...
Remove potential UB from #111576 (move it to importer) + enable more cases where we eliminate write barriers, e.g. this: