[RISC-V] Transfer arguments between calling conventions in shuffling thunks

src/coreclr/vm/callingconvention.h

@@ -642,7 +642,7 @@ class ArgIteratorTemplate : public ARGITERATOR_BASE
     //------------------------------------------------------------
     int GetNextOffset();
 
-    CorElementType GetArgType(TypeHandle *pTypeHandle = NULL)
+    CorElementType GetArgType(TypeHandle *pTypeHandle = NULL) const
     {
         LIMITED_METHOD_CONTRACT;
         if (pTypeHandle != NULL)
@@ -652,7 +652,7 @@ class ArgIteratorTemplate : public ARGITERATOR_BASE
         return m_argType;
     }
 
-    int GetArgSize()
+    int GetArgSize() const
     {
         LIMITED_METHOD_CONTRACT;
         return m_argSize;

src/coreclr/vm/comdelegate.h

@@ -180,11 +180,28 @@ struct ShuffleEntry
         FPREGMASK    = 0x4000, // Floating point register bit
         FPSINGLEMASK = 0x2000, // Single precising floating point register
         OFSMASK      = 0x7fff, // Mask to get stack offset
+#if defined(TARGET_RISCV64)
+        // Whether it's a field of an argument transferred between integer and floating-point calling conventions,
+        // in which case field size and offset are avalilable.
+        CALLCONVTRANSFERMASK = FPSINGLEMASK,
+        OFSREGMASK   = 0x7, // Mask to get register index
+        FIELDSIZESHIFTPOS = 3,
+        FIELDSIZESHIFTMASK = 0x3 << FIELDSIZESHIFTPOS, // Mask to get field log2(size) of FP struct
+        FIELDOFFSETPOS = FIELDSIZESHIFTPOS + 2,
+        FIELDOFFSETMASK = 0xf << FIELDOFFSETPOS, // Mask to get field offset of FP struct
+#else
         OFSREGMASK   = 0x1fff, // Mask to get register index
+#endif // TARGET_RISCV64
         SENTINEL     = 0xffff, // Indicates end of shuffle array
         HELPERREG    = 0xcfff, // Use a helper register as source or destination (used to handle cycles in the shuffling)
     };
 
+#if defined(TARGET_RISCV64)
+    static_assert((OFSREGMASK & FIELDSIZESHIFTMASK) == 0, "must not overlap");
+    static_assert((FIELDSIZESHIFTMASK & FIELDOFFSETMASK) == 0, "must not overlap");
+    static_assert((FIELDOFFSETMASK & (REGMASK | FPREGMASK | CALLCONVTRANSFERMASK)) == 0, "must not overlap");
+#endif
+
     UINT16    srcofs;
 
     union {

src/coreclr/vm/dllimport.h

@@ -202,6 +202,9 @@ enum ILStubTypes
     ILSTUB_TAILCALL_STOREARGS            = 0x80000008,
     ILSTUB_TAILCALL_CALLTARGET           = 0x80000009,
     ILSTUB_STATIC_VIRTUAL_DISPATCH_STUB  = 0x8000000A,
+#ifdef TARGET_RISCV64
+    ILSTUB_DELEGATE_SHUFFLE_THUNK        = 0x8000000B,
+#endif
 };
 
 #ifdef FEATURE_COMINTEROP
@@ -238,6 +241,9 @@ inline bool SF_IsInstantiatingStub      (DWORD dwStubFlags) { LIMITED_METHOD_CON
 #endif
 inline bool SF_IsTailCallStoreArgsStub  (DWORD dwStubFlags) { LIMITED_METHOD_CONTRACT; return (dwStubFlags == ILSTUB_TAILCALL_STOREARGS); }
 inline bool SF_IsTailCallCallTargetStub (DWORD dwStubFlags) { LIMITED_METHOD_CONTRACT; return (dwStubFlags == ILSTUB_TAILCALL_CALLTARGET); }
+#ifdef TARGET_RISCV64
+inline bool SF_IsDelegateShuffleThunk (DWORD dwStubFlags) { LIMITED_METHOD_CONTRACT; return (dwStubFlags == ILSTUB_DELEGATE_SHUFFLE_THUNK); }
+#endif // TARGET_RISCV64
 
 inline bool SF_IsCOMStub               (DWORD dwStubFlags) { LIMITED_METHOD_CONTRACT; return COM_ONLY(dwStubFlags < NDIRECTSTUB_FL_INVALID && 0 != (dwStubFlags & NDIRECTSTUB_FL_COM)); }
 inline bool SF_IsCOMLateBoundStub      (DWORD dwStubFlags) { LIMITED_METHOD_CONTRACT; return COM_ONLY(dwStubFlags < NDIRECTSTUB_FL_INVALID && 0 != (dwStubFlags & NDIRECTSTUB_FL_COMLATEBOUND)); }

src/coreclr/vm/ilstubcache.cpp

@@ -156,6 +156,9 @@ namespace
             case DynamicMethodDesc::StubTailCallStoreArgs:  return "IL_STUB_StoreTailCallArgs";
             case DynamicMethodDesc::StubTailCallCallTarget: return "IL_STUB_CallTailCallTarget";
             case DynamicMethodDesc::StubVirtualStaticMethodDispatch: return "IL_STUB_bVirtualStaticMethodDispatch";
+#ifdef TARGET_RISCV64
+            case DynamicMethodDesc::StubDelegateShuffleThunk: return "IL_STUB_bDelegateShuffleThunk";
+#endif
             default:
                 UNREACHABLE_MSG("Unknown stub type");
         }
@@ -297,6 +300,13 @@ MethodDesc* ILStubCache::CreateNewMethodDesc(LoaderHeap* pCreationHeap, MethodTa
         pMD->SetILStubType(DynamicMethodDesc::StubVirtualStaticMethodDispatch);
     }
     else
+#ifdef TARGET_RISCV64
+    if (SF_IsDelegateShuffleThunk(dwStubFlags))
+    {
+        pMD->SetILStubType(DynamicMethodDesc::StubDelegateShuffleThunk);
+    }
+    else
+#endif // TARGET_RISCV64
     {
         // mark certain types of stub MDs with random flags so ILStubManager recognizes them
         if (SF_IsReverseStub(dwStubFlags))

src/coreclr/vm/method.hpp

@@ -2512,6 +2512,7 @@ class DynamicMethodDesc : public StoredSigMethodDesc
         StubTailCallCallTarget,
 
         StubVirtualStaticMethodDispatch,
+        StubDelegateShuffleThunk,
 
         StubLast
     };

src/coreclr/vm/riscv64/cgencpu.h

@@ -360,15 +360,6 @@ struct FloatReg
     WORD Mask() const { return 1 << reg; }
 };
 
-struct CondCode
-{
-    int cond;
-    CondCode(int cond):cond(cond)
-    {
-        _ASSERTE(0 <= cond && cond < 16);
-    }
-};
-
 const IntReg RegSp  = IntReg(2);
 const IntReg RegFp  = IntReg(8);
 const IntReg RegRa  = IntReg(1);
@@ -392,6 +383,7 @@ class StubLinkerCPU : public StubLinker
     void EmitCallLabel(CodeLabel *target, BOOL fTailCall, BOOL fIndirect);
 
     void EmitShuffleThunk(struct ShuffleEntry *pShuffleEntryArray);
+    void EmitShufflingWithCallingConventionTransfers(const struct ShuffleEntry *pShuffleEntryArray);
 
 #if defined(FEATURE_SHARE_GENERIC_CODE)
     void EmitComputedInstantiatingMethodStub(MethodDesc* pSharedMD, struct ShuffleEntry *pShuffleEntryArray, void* extraArg);
@@ -402,15 +394,18 @@ class StubLinkerCPU : public StubLinker
     void EmitMovReg(IntReg dest, IntReg source);
     void EmitMovReg(FloatReg dest, FloatReg source);
 
-    void EmitSubImm(IntReg Xd, IntReg Xn, unsigned int value);
-    void EmitAddImm(IntReg Xd, IntReg Xn, unsigned int value);
+    void EmitSubImm(IntReg Xd, IntReg Xn, int value);
+    void EmitAddImm(IntReg Xd, IntReg Xn, int value);
     void EmitSllImm(IntReg Xd, IntReg Xn, unsigned int value);
     void EmitLuImm(IntReg Xd, unsigned int value);
 
     void EmitLoad(IntReg dest, IntReg srcAddr, int offset = 0);
     void EmitLoad(FloatReg dest, IntReg srcAddr, int offset = 0);
+    void EmitAnyLoad(bool isFloat, unsigned int sizeShift, int destReg, IntReg srcAddr, int offset = 0);
+
     void EmitStore(IntReg src, IntReg destAddr, int offset = 0);
     void EmitStore(FloatReg src, IntReg destAddr, int offset = 0);
+    void EmitAnyStore(bool isFloat, unsigned int sizeShift, int srcReg, IntReg destAddr, int offset = 0);
 
     void EmitProlog(unsigned short cIntRegArgs, unsigned short cFpRegArgs, unsigned short cbStackSpace = 0);
     void EmitEpilog();