ARM64-SVE: Add MultiplyAddRotateComplexBySelectedScalar

[amanasifkhalid]

Part of #99957. I had to add a new test template to cover APIs with three vector args, and two immediates; the new template is identical to _SveImmTernOpTestTemplate.template, except that I added additional Imm and InvalidImm arguments. JIT changes are a bit more involved for this API because it is the first ARM64 intrinsic with five operands. This means the HWIntrinsic struct now has an additional GenTree* member. If the TP impact of this is too high, I can get rid of the new member; the code for handling the fifth operand will look a bit less elegant, but it's only for this API, for now.

With @kunalspathak's fix in #104998 merged in locally, all stress tests pass. The SVE encoding unit tests passed, too (I had to tweak the emitter and tests to take the rotation value in its encoded form to match the API-level behavior). Since the jump table generation is a bit odd for this API, here's what the codegen looks like:

G_M19160_IG01:  ;; offset=0x0000
            stp     fp, lr, [sp, #-0x10]!
            mov     fp, sp
                                                ;; size=8 bbWeight=1 PerfScore 1.50
G_M19160_IG02:  ;; offset=0x0008
            uxtb    w0, w0
            cmp     w0, #2
            bhs     G_M19160_IG13
            uxtb    w1, w1
            cmp     w1, #4
            bhs     G_M19160_IG13
            lsl     w1, w1, #1
            orr     w0, w0, w1
            adr     x2, [G_M19160_IG03]
            add     x2, x2, x0,  LSL #3
            br      x2
                                                ;; size=44 bbWeight=1 PerfScore 8.00
G_M19160_IG03:  ;; offset=0x0034
            fcmla   z0.s, z1.s, z2.s[0], #0
            b       G_M19160_IG11
                                                ;; size=8 bbWeight=1 PerfScore 5.00
G_M19160_IG04:  ;; offset=0x003C
            fcmla   z0.s, z1.s, z2.s[1], #0
            b       G_M19160_IG11
                                                ;; size=8 bbWeight=1 PerfScore 5.00
G_M19160_IG05:  ;; offset=0x0044
            fcmla   z0.s, z1.s, z2.s[0], #90
            b       G_M19160_IG11
                                                ;; size=8 bbWeight=1 PerfScore 5.00
G_M19160_IG06:  ;; offset=0x004C
            fcmla   z0.s, z1.s, z2.s[1], #90
            b       G_M19160_IG11
                                                ;; size=8 bbWeight=1 PerfScore 5.00
G_M19160_IG07:  ;; offset=0x0054
            fcmla   z0.s, z1.s, z2.s[0], #180
            b       G_M19160_IG11
                                                ;; size=8 bbWeight=1 PerfScore 5.00
G_M19160_IG08:  ;; offset=0x005C
            fcmla   z0.s, z1.s, z2.s[1], #180
            b       G_M19160_IG11
                                                ;; size=8 bbWeight=1 PerfScore 5.00
G_M19160_IG09:  ;; offset=0x0064
            fcmla   z0.s, z1.s, z2.s[0], #270
            b       G_M19160_IG11
                                                ;; size=8 bbWeight=1 PerfScore 5.00
G_M19160_IG10:  ;; offset=0x006C
            fcmla   z0.s, z1.s, z2.s[1], #270
                                                ;; size=4 bbWeight=1 PerfScore 4.00
G_M19160_IG11:  ;; offset=0x0070
            and     w0, w0, #1
            lsr     w1, w1, #1
                                                ;; size=8 bbWeight=1 PerfScore 1.50
G_M19160_IG12:  ;; offset=0x0078
            ldp     fp, lr, [sp], #0x10
            ret     lr
                                                ;; size=8 bbWeight=1 PerfScore 2.00
G_M19160_IG13:  ;; offset=0x0080
            bl      CORINFO_HELP_THROW_ARGUMENTOUTOFRANGEEXCEPTION
            brk_windows #0
                                                ;; size=8 bbWeight=0 PerfScore 0.00

@dotnet/arm64-contrib PTAL, thanks!

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[dotnet-issue-labeler]

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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[kunalspathak]

This should have HW_Category_SIMDByIndexedElement.

[amanasifkhalid]

I agree that category makes sense, though this API seems different enough from other HW_Category_SIMDByIndexedElement APIs that we would have to add several special cases on that category's path (for example, all the 5-operand handling, plus the fact that we index the third vector register in pairs of elements, so the default bounds calculation for the index doesn't work). Do we want to move this logic over?

[kunalspathak]

synced offline...ok to skip this but to add a comment in lsraarm64.cpp explaining why we do not mark it such and why we just need 1 internal register although we have 2 immediates.

[kunalspathak]

can you please monitor the TP cost and also check the memory cost by adding op5?

[amanasifkhalid]

can you please monitor the TP cost and also check the memory cost by adding op5?

Sure: Looks like the TP cost is trivial. Is there a tool we use to measure diffs in memory usage?

[kunalspathak]

Is there a tool we use to measure diffs in memory usage?

ignore that. we have updated the struct which gets allocated on the stack and not from arena allocator.

[kunalspathak]

LGTM. Thanks!

[amanasifkhalid]

/ba-g blocking failures are timeouts