Add support for Sve.DuplicateSelectedScalarToVector() #103228

SwapnilGaikwad · 2024-06-10T14:28:01Z

Contribute towards #99957.

dotnet-issue-labeler · 2024-06-10T14:28:06Z

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dotnet-issue-labeler · 2024-06-10T14:28:07Z

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SwapnilGaikwad · 2024-06-10T14:40:14Z

@a74nh @kunalspathak @dotnet/arm64-contrib @arch-arm64-sve

SwapnilGaikwad · 2024-06-10T15:09:13Z

There are a few assertion failures, related to STR. Taking a further look.

Stress test results

===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_float() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_double() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_sbyte() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_short() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_int() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_long() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_byte() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_ushort() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_uint() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_ulong() : 17
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
Errors:

Assert failure(PID 2894704 [0x002c2b70], Thread: 2894704 [0x2c2b70]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Program:SveDuplicateSelectedScalarToVector_double()' during 'Generate code' (IL size 115; hash 0x749c6f16; FullOpts)

    File: /home/user/dotnet/runtime/src/coreclr/jit/emitarm64sve.cpp:14192
    Image: /home/user/dotnet/runtime/artifacts/tests/coreclr/linux.arm64.Checked/Tests/Core_Root/corerun


------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
Errors:

Assert failure(PID 2894838 [0x002c2bf6], Thread: 2894838 [0x2c2bf6]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Program:SveDuplicateSelectedScalarToVector_double()' during 'Generate code' (IL size 115; hash 0x749c6f16; FullOpts)

    File: /home/user/dotnet/runtime/src/coreclr/jit/emitarm64sve.cpp:14192
    Image: /home/user/dotnet/runtime/artifacts/tests/coreclr/linux.arm64.Checked/Tests/Core_Root/corerun


------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

kunalspathak · 2024-06-10T16:31:11Z

related to STR.

I have seen them in the past, but yes, if you can find out what is the cause, that will be good.

SwapnilGaikwad · 2024-06-11T14:06:49Z

All stress tests are passing now.

Stress test results

===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_float() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_double() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_sbyte() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_short() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_int() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_long() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_byte() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_ushort() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_uint() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveDuplicateSelectedScalarToVector_ulong() : 17
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

kunalspathak

Added few things to check.

kunalspathak · 2024-06-11T18:21:36Z

src/coreclr/jit/hwintrinsicarm64.cpp

@@ -421,6 +421,10 @@ void HWIntrinsicInfo::lookupImmBounds(
                immUpperBound = (int)SVE_PATTERN_ALL;
                break;

+            case NI_Sve_DuplicateSelectedScalarToVector:
+                immUpperBound = (512 / (genTypeSize(baseType) * BITS_PER_BYTE)) - 1;


Suggested change

immUpperBound = (512 / (genTypeSize(baseType) * BITS_PER_BYTE)) - 1;

immUpperBound = Compiler::getSIMDVectorLength(simdSize, baseType) - 1;

We may not able able to use the getSIMDVectorLength() here as the imm for DUP seems special [1].

Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".

I didn't find a better helper method for this so did it explicitly.

I was actually little confused with that description and then this one:

The immediate element index is in the range of 0 to 63 (bytes), 31 (halfwords), 15 (words), 7 (doublewords) or 3 (quadwords).

With ^ description, it sounded me like getSIMDVectorLength(), no?

It's a bit confusing. Unlike other cases, the index here does not depend on the vector length. A valid index range is fixed based on the element type, e.g., 0 to 63 for vectors of type byte.

kunalspathak · 2024-06-11T18:23:59Z

src/tests/JIT/HardwareIntrinsics/Arm/Shared/_SveImmUnaryOpTestTemplate.template

+            ValidateResult(_dataTable.inArrayPtr, {Imm}, _dataTable.outArrayPtr);
+        }
+
+        public void RunBasicScenario_UnsafeRead_InvalidImm()


can you confirm what is the behavior here?

From https://docsmirror.github.io/A64/2023-06/dup_z_zi.html, is it validating this portion:

Selecting an element beyond the accessible vector length causes the destination vector to be set to zero.

Invalid index refers to a value that is permitted but out of bounds on the current system. E.g., bytes permitted index values are between 0 to 63 but on a 256bit SVE length machine, valid indices can be between 256 / 8 - 1 = 0 to 31. Thus, the indices between 32 to 63 would set the destination value to zero.

src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs

src/coreclr/jit/emitarm64.cpp

src/coreclr/jit/hwintrinsiclistarm64sve.h

src/coreclr/jit/hwintrinsiccodegenarm64.cpp

SwapnilGaikwad · 2024-06-20T14:44:50Z

The tests with short are failing with the following assertion error. Not sure if it's related to the patch.
Do you have any suggestions on how to fix them?

Beginning scenario: RunBasicScenario_UnsafeRead

Assert failure(PID 1069122 [0x00105042], Thread: 1069122 [0x105042]): Assertion failed '(candidates & allRegs(regType)) != RBM_NONE' in 'System.Runtime.Intrinsics.Arm.Sve:DuplicateSelectedScalarToVector(System.Numerics.Vector`1[short],ubyte):System.Numerics.Vector`1[short]' during 'LSRA build intervals' (IL size 8; hash 0x3d7d92ae; Tier0)

    File: /home/user/dotnet/runtime/src/coreclr/jit/lsra.cpp:2913
    Image: /home/user/dotnet/runtime/dup-artifacts/tests/coreclr/linux.arm64.Checked/Tests/Core_Root/corerun

Aborted (core dumped)

SwapnilGaikwad · 2024-06-20T15:57:35Z

JIT dump for a failing method.

kunalspathak · 2024-06-20T16:04:24Z

JIT dump for a failing method.

@SwapnilGaikwad - Are you sure this one is the right dump? I see the compilation succeed in this dump.

kunalspathak · 2024-06-20T16:05:58Z

Do you have any suggestions on how to fix them?

This is to do with that a node is of type TYP_FLOAT and we assigned it candidates of TYP_MASK or vice-versa. It might not be directly related to your PR, but something that your PR exposed specially after the LSRA work of predicate register is complete. If you share the correct dump, I can quickly tell for which node it is getting wrong, and you can then track in lsraarm64.cpp why that is happening.

SwapnilGaikwad · 2024-06-21T10:22:53Z

Hi Kunal, apologies. It was dump of the parent test method that emitted a call to Sve.DuplicateSelectedScalarToVector.
I have updated the gist with the correct dump now.

kunalspathak · 2024-06-21T14:05:43Z

Hi Kunal, apologies. It was dump of the parent test method that emitted a call to Sve.DuplicateSelectedScalarToVector. I have updated the gist with the correct dump now.

DefList: { N004.t0. LCL_VAR; N014.t1. LCL_VAR }
N016 (  4,  4) [000009] -----------                         *  CAST      int <- ubyte <- int REG NA
<RefPosition #7   @16  RefTypeUse <Ivl:3> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval  4: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #8   @17  RefTypeDef <Ivl:4> CAST BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N004.t0. LCL_VAR; N016.t9. CAST }
N018 ( 17, 20) [000006] ---X-------                         *  HWINTRINSIC simd16 short DuplicateSelectedScalarToVector REG NA
Interval  5: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #9   @18  RefTypeDef <Ivl:5 internal> HWINTRINSIC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #10  @18  RefTypeUse <Ivl:0> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #11  @18  RefTypeUse <Ivl:4> BB01 regmask=[d0-d15] minReg=1 last wt=100.00>
<RefPosition #12  @18  RefTypeUse <Ivl:5 internal> HWINTRINSIC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
Interval  6: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #13  @19  RefTypeDef <Ivl:6> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>

I think the problem is in <Ivl:4>. For def RefPosition #8, the mask created is GPR, but the use RefPosition #11, the mask if d0-d15 which is GPR, which seems wrong. So, you might want to check by putting breakpoint in newRefPositionRaw() for newRP->rpNum == 11 why the mask is not gpr.

kunalspathak · 2024-06-25T19:09:35Z

@SwapnilGaikwad - I assume you don't need anything from me for this PR?

SwapnilGaikwad · 2024-06-26T09:00:05Z

@SwapnilGaikwad - I assume you don't need anything from me for this PR?

Hi @kunalspathak , I haven't exhausted all the debugging possibilities yet. I might come back with questions 🙂 .

SwapnilGaikwad · 2024-06-26T17:37:13Z

why the mask is not gpr

Hi @kunalspathak , your suggestion was very useful to identify the issue. The mask was hardcoded to simd registers for op2.

All stress tests pass

===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_float() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_double() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_sbyte() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_short() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_int() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_long() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_byte() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_ushort() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_uint() : 17
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_DuplicateSelectedScalarToVector_ulong() : 17
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

src/coreclr/jit/lsraarm64.cpp

kunalspathak

Looks good overall. Have a question about the change in codegenarm64.cpp.

Also, how are we exposing DUP (immediate) and DUP (scalar) ?

kunalspathak · 2024-06-27T13:54:54Z

src/coreclr/jit/emitarm64.cpp

@@ -8150,9 +8153,11 @@ void emitter::emitIns_S_R(instruction ins, emitAttr attr, regNumber reg1, int va
            {
                useRegForImm      = true;
                regNumber rsvdReg = codeGen->rsGetRsvdReg();
-                codeGen->instGen_Set_Reg_To_Imm(EA_PTRSIZE, rsvdReg, imm);
+                // For larger imm values (> 9 bits), calculate base + imm in a reserved register first.
+                codeGen->instGen_Set_Reg_To_Base_Plus_Imm(EA_PTRSIZE, rsvdReg, reg2, imm);


Is this change related to the DUP? Don't think so.

I might actually need it for https://github.com/dotnet/runtime/pull/104065/files#diff-2b2c8b9011607926410624d6f81613fad7b74c6e0516d578675a8b792998fe4fR7893-R7896, but I am curious if you found a repro, for which you had to add change here.

This is not related to DUP directly. However, tests trigger a scenario where we end up in having a store with a larger immediate.

kunalspathak · 2024-06-27T15:08:30Z

Also, how are we exposing DUP (immediate) and DUP (scalar) ?

Spoke offline that we will use these in future when we intrinsify Vector.Create or similar scenario for sve.

kunalspathak

LGTM

Add support for Sve.DuplicateScalarToVector()

66dca24

dotnet-issue-labeler bot added area-System.Runtime.Intrinsics new-api-needs-documentation labels Jun 10, 2024

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Fix build errors from API mismatch

98208f6

SwapnilGaikwad added 2 commits June 10, 2024 16:27

Use ConstantExpected instead of ConstantExpectedAttribute

39f4a31

Fix API incompatibility in Sve.PlatformNotSupported.cs

76acc39

kunalspathak added the arm-sve Work related to arm64 SVE/SVE2 support label Jun 10, 2024

kunalspathak changed the title ~~Add support for Sve.DuplicateScalarToVector()~~ Add support for Sve.DuplicateSelectedScalarToVector() Jun 10, 2024

kunalspathak mentioned this pull request Jun 10, 2024

Arm64: Implement SVE APIs #99957

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Fix emitting larger than 9-bit immediate with Sve LDR/STR instructions

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Add HW_Category_SIMDByIndexedElement flag

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Fix issue for getting incorrect register type for op2

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Add support for Sve.DuplicateSelectedScalarToVector() #103228

Add support for Sve.DuplicateSelectedScalarToVector() #103228

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	immUpperBound = (512 / (genTypeSize(baseType) * BITS_PER_BYTE)) - 1;
	immUpperBound = Compiler::getSIMDVectorLength(simdSize, baseType) - 1;

Add support for Sve.DuplicateSelectedScalarToVector() #103228

Add support for Sve.DuplicateSelectedScalarToVector() #103228

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