ARM64-SVE: GetActiveElementCount

[a74nh]

Also added some Helper functions to get random data for a mask element. These can eventually be used in existing templates.

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[a74nh]

@dotnet/arm64-contrib @kunalspathak This is ready now

[kunalspathak]

What cannot we handle op2 handling next to the place where we handle op1?

[a74nh]

that would require an if (id ==NI_Sve_GetActiveElementCount) in hwintrinsic.cpp. I'm trying to avoid adding any Arm specific code in that file.

[kunalspathak]

currently we have this:

    if (HWIntrinsicInfo::IsExplicitMaskedOperation(intrinsic))
    {
        assert(numArgs > 0);
        GenTree* op1 = retNode->AsHWIntrinsic()->Op(1);
        if (intrinsic == NI_Sve_ConditionalSelect)
        {
            if (op1->IsVectorAllBitsSet() || op1->IsMaskAllBitsSet())
            {
                return retNode->AsHWIntrinsic()->Op(2);
            }
            else if (op1->IsVectorZero())
            {
                return retNode->AsHWIntrinsic()->Op(3);
            }
        }

        if (!varTypeIsMask(op1))
        {
            // Op1 input is a vector. HWInstrinsic requires a mask.
            retNode->AsHWIntrinsic()->Op(1) = gtNewSimdConvertVectorToMaskNode(retType, op1, simdBaseJitType, simdSize);
        }
}

we can have varTypeIsMask(op2) after the op1, right?

[a74nh]

Yes, but would still require a NI_Sve_GetActiveElementCount check, as we don't want to convert for other nodes.

[kunalspathak]

hhm, are there many intrinsic that will have op2 as mask? we can add assert or something to make sure that it is NI_Sve_GetActiveElementCount.

[a74nh]

I've simplified this handling. There's now just a small extra bit in IsExplicitMaskedOperation()

[kunalspathak]

LGTM

[kunalspathak]

/ba-g build errors are timeout