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NativeAOT/linux/arm: Fix native linux/arm failure #102760

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merged 1 commit into from
May 29, 2024
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NativeAOT/linux/arm: Fix native linux/arm failure #102760

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16 changes: 11 additions & 5 deletions src/coreclr/jit/target.h
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Original file line number Diff line number Diff line change
Expand Up @@ -356,24 +356,30 @@ static bool operator>(regMaskTP first, regMaskTP second)
return first.getLow() > second.getLow();
}

static regMaskTP operator<<(regMaskTP& first, const int b)
static regMaskTP operator<<(regMaskTP first, const int b)
{
regMaskTP result(first.getLow() << b);
return result;
}

static regMaskTP operator>>(regMaskTP& first, const int b)
static regMaskTP& operator<<=(regMaskTP& first, const int b)
{
first = first << b;
return first;
}
#endif

static regMaskTP operator>>(regMaskTP first, const int b)
{
regMaskTP result(first.getLow() >> b);
return result;
}

static regMaskTP& operator<<=(regMaskTP& first, const int b)
static regMaskTP& operator>>=(regMaskTP& first, const int b)
{
first = first << b;
first = first >> b;
return first;
}
#endif

static regMaskTP operator~(regMaskTP first)
{
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3 changes: 2 additions & 1 deletion src/coreclr/jit/unwind.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -224,11 +224,12 @@ void Compiler::unwindPushPopMaskCFI(regMaskTP regMask, bool isFloat)
// because LLVM only know about D0-D31.
// As such pairs Sx,Sx+1 are referenced as D0-D15 registers in DWARF
// For that we process registers in pairs.
regBit >>= isFloat ? 2 : 1;
regNum = isFloat ? REG_PREV(REG_PREV(regNum)) : REG_PREV(regNum);
#else
regBit >>= 1;
regNum = REG_PREV(regNum);
#endif
regBit = genRegMask(regNum);
}
}

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