also adjust the LSRA for SIMD registers

src/coreclr/jit/lsraarmarch.cpp

@@ -212,7 +212,7 @@ int LinearScan::BuildCall(GenTreeCall* call)
         // the target. We do not handle these constraints on the same
         // refposition too well so we help ourselves a bit here by forcing the
         // null check with LR.
-        regMaskTP candidates = call->IsFastTailCall() ? RBM_LR : 0;
+        regMaskTP candidates = call->IsFastTailCall() ? RBM_LR : RBM_NONE;
         buildInternalIntRegisterDefForNode(call, candidates);
     }
 #endif // TARGET_ARM
@@ -634,7 +634,7 @@ int LinearScan::BuildBlockStore(GenTreeBlk* blkNode)
 
                 const bool isDstRegAddrAlignmentKnown = dstAddr->OperIsLocalAddr();
 
-                if (isDstRegAddrAlignmentKnown && (size > FP_REGSIZE_BYTES))
+                if (/*isDstRegAddrAlignmentKnown && */(size > FP_REGSIZE_BYTES))
                 {
                     // For larger block sizes CodeGen can choose to use 16-byte SIMD instructions.
                     buildInternalFloatRegisterDefForNode(blkNode, internalFloatRegCandidates());
@@ -713,7 +713,7 @@ int LinearScan::BuildBlockStore(GenTreeBlk* blkNode)
                     // CodeGen can use 16-byte SIMD ldp/stp for larger block sizes
                     // only when both source and destination base address registers have known alignment.
                     // This is the case, when both registers are either sp or fp.
-                    bool canUse16ByteWideInstrs = isSrcAddrLocal && isDstAddrLocal && (size >= 2 * FP_REGSIZE_BYTES);
+                    bool canUse16ByteWideInstrs = /*isSrcAddrLocal && isDstAddrLocal &&*/ (size >= 2 * FP_REGSIZE_BYTES);
 
                     // Note that the SIMD registers allocation is speculative - LSRA doesn't know at this point
                     // whether CodeGen will use SIMD registers (i.e. if such instruction sequence will be more optimal).