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[WIP] Spin Wait tuning #13527
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[WIP] Spin Wait tuning #13527
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@kouvel PTAL. This is work in progress. I'd like to hear your feedback before I try something more. |
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Closing stale PRs. The issue that this is trying to fix is closed. It has been fixed by other changes already. |
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Work in progress. https://github.com/dotnet/coreclr/issues/13388
This PR tries to tune the Spin Wait on AMD64 and X86 platforms. Because "The latency of PAUSE instruction in prior generation microarchitecture is about 10 cycles, whereas on Skylake microarchitecture it has been extended to as many as 140 cycles."
Assume
YieldProcessor()took 10 cycles when the original code was written and tuned.get_cycle_count()is defined asrdtsc.Use the similar method, which is suggested by the example shown at https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf