mediatek: add Airoha AN8855 gigabit switch driver

New revisions of Xiaomi AX3000T with 1.0.84+ stock firmware contain new hardware. This commit add support for Airoha AN8855 gigabit switch driver with 6.6 kernel patches Based on https://patchwork.kernel.org/project/netdevbpf/cover/[email protected]/ Signed-off-by: Dim Fish <[email protected]>
dimfishr · Nov 30, 2024 · 06841e3 · 06841e3
1 parent af611bc
commit 06841e3
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diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi
@@ -83,6 +83,14 @@
 		interrupt-parent = <&pio>;
 		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+	switch2: switch@1 {
+		compatible = "airoha,an8855";
+		reg = <1>;
+		reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+		airoha,ext-surge;
+		#nvmem-cell-cells = <0>;
+	};
 };
 
 &switch {
@@ -124,6 +132,169 @@
 	};
 };
 
+&switch2 {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
+			reg = <0xc 0x4>;
+		};
+
+		shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
+			reg = <0x10 0x4>;
+		};
+
+		shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
+			reg = <0x14 0x4>;
+		};
+
+		shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
+			reg = <0x18 0x4>;
+		};
+
+		shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
+			reg = <0x1c 0x4>;
+		};
+
+		shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
+			reg = <0x20 0x4>;
+		};
+
+		shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
+			reg = <0x24 0x4>;
+		};
+
+		shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
+			reg = <0x28 0x4>;
+		};
+
+		shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
+			reg = <0x2c 0x4>;
+		};
+
+		shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
+			reg = <0x30 0x4>;
+		};
+
+		shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
+			reg = <0x34 0x4>;
+		};
+
+		shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
+			reg = <0x38 0x4>;
+		};
+
+		shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
+			reg = <0x4c 0x4>;
+		};
+
+		shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
+			reg = <0x50 0x4>;
+		};
+
+		shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
+			reg = <0x54 0x4>;
+		};
+
+		shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
+			reg = <0x58 0x4>;
+		};
+	};
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "wan";
+			phy-mode = "internal";
+			phy-handle = <&internal_phy1>;
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+			phy-mode = "internal";
+			phy-handle = <&internal_phy2>;
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+			phy-mode = "internal";
+			phy-handle = <&internal_phy3>;
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+			phy-mode = "internal";
+			phy-handle = <&internal_phy4>;
+		};
+
+		port@5 {
+			reg = <5>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		internal_phy1: phy@1 {
+			reg = <1>;
+
+			nvmem-cells = <&shift_sel_port0_tx_a>,
+					<&shift_sel_port0_tx_b>,
+					<&shift_sel_port0_tx_c>,
+					<&shift_sel_port0_tx_d>;
+			nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+		};
+
+		internal_phy2: phy@2 {
+			reg = <2>;
+
+			nvmem-cells = <&shift_sel_port1_tx_a>,
+					<&shift_sel_port1_tx_b>,
+					<&shift_sel_port1_tx_c>,
+					<&shift_sel_port1_tx_d>;
+			nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+		};
+
+		internal_phy3: phy@3 {
+			reg = <3>;
+
+			nvmem-cells = <&shift_sel_port2_tx_a>,
+					<&shift_sel_port2_tx_b>,
+					<&shift_sel_port2_tx_c>,
+					<&shift_sel_port2_tx_d>;
+			nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+		};
+
+		internal_phy4: phy@4 {
+			reg = <4>;
+
+			nvmem-cells = <&shift_sel_port3_tx_a>,
+					<&shift_sel_port3_tx_b>,
+					<&shift_sel_port3_tx_c>,
+					<&shift_sel_port3_tx_d>;
+			nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+		};
+	};
+};
+
 &spi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi0_flash_pins>;