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SIGMA RTL Author: Eric Qin Contact: [email protected] *** Under construction *** SIGMA Flex-DPE RTL. Compile verilog files: Run "make clean test" Open Waveform Viewer: Run "make dve" High level details can be found in the powerpoint.
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RTL implementation of Flex-DPE.
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- Verilog 59.3%
- Python 35.4%
- SystemVerilog 4.7%
- Other 0.6%