Q2.2023
Release notes:
- Two PRs merged:
- Major update to the chapter 3 CPU-Microarchitecture
- DRAM rank, channels, interleaving
- Multicore, SMT, and Hybrid CPUs.
- Branch prediction section.
- Updated section "Modern CPU design" (Skylake -> Goldencove), deep dive into CPU Front-End, Back-End, Load-Store unit, and TLB hierarchy.
- Added questions and exercises throughout the book.
- Major rewrite of section 6.1 Code Instrumentation.
- Updated intro for the second part (section 9.0).
- Split previously chapter 9 BackendBound into two: chapter 9 MemoryBound and chapter 10 CoreBound.