rockchip: fix kernel 5.10 build error

target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2021 Tianling Shen <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R2C";
+	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
+};
+
+&gmac2io {
+	phy-handle = <&yt8521s>;
+
+	mdio {
+		/delete-node/ ethernet-phy@1;
+
+		yt8521s: ethernet-phy@3 {
+			compatible = "ethernet-phy-id0000.011a",
+				     "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+			pinctrl-0 = <&eth_phy_reset_pin>;
+			pinctrl-names = "default";
+			reset-assert-us = <10000>;
+			reset-deassert-us = <50000>;
+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&lan_led {
+	label = "nanopi-r2c:green:lan";
+};
+
+&sys_led {
+	label = "nanopi-r2c:red:sys";
+};
+
+&wan_led {
+	label = "nanopi-r2c:green:wan";
+};

target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts

@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus LTS";
+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
+
+/delete-node/ &rtl8211e;
+&gmac2io {
+        phy-handle = <&ethphy3>;
+        snps,reset-delays-us = <0 15000 50000>;
+        tx_delay = <0x19>;
+        rx_delay = <0x05>;
+        status = "okay";
+
+        mdio {
+                compatible = "snps,dwmac-mdio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy3: ethernet-phy@0 {
+                        reg = <0x0>;
+                        keep-clkout-on;
+                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&sdmmc {
+      bus-width = <4>;
+      cap-sd-highspeed;
+      disable-wp;
+      pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+      pinctrl-names = "default";
+      sd-uhs-sdr12;
+      sd-uhs-sdr25;
+      sd-uhs-sdr50;
+      sd-uhs-sdr104;
+      vmmc-supply = <&vcc_sd>;
+      vqmmc-supply = <&vcc_io_sdio>;
+      status = "okay";
+};
+
+&dmc_opp_table {
+        opp-1056000000 {
+                status = "disabled";
+        };
+        opp-924000000 {
+                status = "disabled";
+        };
+        opp-840000000 {
+                status = "disabled";
+        };
+        opp-798000000 {
+                status = "disabled";
+        };
+};
+
+&sys_led {
+       label = "orangepi-r1-plus-lts:red:sys";
+};
+
+&wan_led {
+       label = "orangepi-r1-plus-lts:green:wan";
+};
+
+&lan_led {
+       label = "orangepi-r1-plus-lts:green:lan";
+};

target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus";
+	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
+};
+
+&lan_led {
+	label = "orangepi-r1-plus:green:lan";
+};
+
+&spi0 {
+	max-freq = <48000000>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&sys_led {
+	gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+	label = "orangepi-r1-plus:red:sys";
+};
+
+&sys_led_pin {
+	rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&wan_led {
+	label = "orangepi-r1-plus:green:wan";
+};

target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+
+/dts-v1/;
+/ {
+	model = "FriendlyElec NanoPi R5S";
+	compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
+};

target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+/ {
+	model = "FastRhino R66S";
+	compatible = "fastrhino,r66s", "rockchip,rk3568";
+};
+

target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+/ {
+	model = "Radxa ROCK3 Model A";
+	compatible = "radxa,rock3a", "rockchip,rk3568";
+};

target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+/ {
+	model = "Firefly Station P2";
+	compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
+};

target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch

@@ -7,46 +7,4 @@
 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,39 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+	model = "Xunlong Orange Pi R1 Plus";
-+	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-+};
-+
-+&lan_led {
-+	label = "orangepi-r1-plus:green:lan";
-+};
-+
-+&spi0 {
-+	max-freq = <48000000>;
-+	status = "okay";
-+
-+	flash@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <10000000>;
-+	};
-+};
-+
-+&sys_led {
-+	gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-+	label = "orangepi-r1-plus:red:sys";
-+};
-+
-+&sys_led_pin {
-+	rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+};
-+
-+&uart1 {
-+	status = "okay";
-+};
-+
-+&wan_led {
-+	label = "orangepi-r1-plus:green:wan";
-+};
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb

target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch

@@ -7,54 +7,4 @@
 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-@@ -0,0 +1,47 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2021 Tianling Shen <[email protected]>
-+ */
-+
-+/dts-v1/;
-+
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+	model = "FriendlyElec NanoPi R2C";
-+	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+	phy-handle = <&yt8521s>;
-+
-+	mdio {
-+		/delete-node/ ethernet-phy@1;
-+
-+		yt8521s: ethernet-phy@3 {
-+			compatible = "ethernet-phy-id0000.011a",
-+				     "ethernet-phy-ieee802.3-c22";
-+			reg = <3>;
-+			pinctrl-0 = <&eth_phy_reset_pin>;
-+			pinctrl-names = "default";
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <50000>;
-+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
-+
-+&lan_led {
-+	label = "nanopi-r2c:green:lan";
-+};
-+
-+&sys_led {
-+	label = "nanopi-r2c:red:sys";
-+};
-+
-+&wan_led {
-+	label = "nanopi-r2c:green:wan";
-+};
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb

target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch

@@ -20,82 +20,4 @@ index 23373c752..552d97555 100644
 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-new file mode 100644
-index 000000000..c65f7c417
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -0,0 +1,70 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+#include "rk3328-orangepi-r1-plus.dts"
-+
-+/ {
-+	model = "Xunlong Orange Pi R1 Plus LTS";
-+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-+};
-+
-+/delete-node/ &rtl8211e;
-+&gmac2io {
-+        phy-handle = <&ethphy3>;
-+        snps,reset-delays-us = <0 15000 50000>;
-+        tx_delay = <0x19>;
-+        rx_delay = <0x05>;
-+        status = "okay";
-+
-+        mdio {
-+                compatible = "snps,dwmac-mdio";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+
-+                ethphy3: ethernet-phy@0 {
-+                        reg = <0x0>;
-+                        keep-clkout-on;
-+                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+                };
-+        };
-+};
-+
-+&sdmmc {
-+      bus-width = <4>;
-+      cap-sd-highspeed;
-+      disable-wp;
-+      pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+      pinctrl-names = "default";
-+      sd-uhs-sdr12;
-+      sd-uhs-sdr25;
-+      sd-uhs-sdr50;
-+      sd-uhs-sdr104;
-+      vmmc-supply = <&vcc_sd>;
-+      vqmmc-supply = <&vcc_io_sdio>;
-+      status = "okay";
-+};
-+
-+&dmc_opp_table {
-+        opp-1056000000 {
-+                status = "disabled";
-+        };
-+        opp-924000000 {
-+                status = "disabled";
-+        };
-+        opp-840000000 {
-+                status = "disabled";
-+        };
-+        opp-798000000 {
-+                status = "disabled";
-+        };
-+};
-+
-+&sys_led {
-+       label = "orangepi-r1-plus-lts:red:sys";
-+};
-+
-+&wan_led {
-+       label = "orangepi-r1-plus-lts:green:wan";
-+};
-+
-+&lan_led {
-+       label = "orangepi-r1-plus-lts:green:lan";
-+};
--- 
-2.25.1
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb