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Revert "Skip failing test-suite CI on 1.8"
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This reverts commit a847d37.
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DigitalBrains1 committed Sep 7, 2024
1 parent c0ee7d7 commit 187a87c
Showing 1 changed file with 1 addition and 23 deletions.
24 changes: 1 addition & 23 deletions test-suite/Main.hs
Original file line number Diff line number Diff line change
Expand Up @@ -185,41 +185,24 @@ runClashTest = defaultMain $ clashTestRoot
]
}
in runTest "Floating" _opts

-- "Unmatchable constant as case subject"
#if MIN_VERSION_clash_lib(1,9,0)
, runTest "XpmCdcArraySingle" $ def
{ hdlTargets=[VHDL, Verilog]
, hdlLoad=[Vivado]
, hdlSim=[Vivado]
, buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
}
#endif

, runTest "XpmCdcGray" $ def
{ hdlTargets=[VHDL, Verilog]
, hdlLoad=[Vivado]
, hdlSim=[Vivado]
, buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
}
, runTest "XpmCdcHandshake" $ def
{ hdlTargets=
[

-- (Vivado) ERROR: [VRFC 10-2989] 'tuple3_0_sel0_std_logic_vector' is not declared [/tmp/clash-test_XpmCdcHandshake-71223bd02c6e132d/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:122]
#if MIN_VERSION_clash_lib(1,9,0)
VHDL,
#endif

Verilog
]
{ hdlTargets=[VHDL, Verilog]
, hdlLoad=[Vivado]
, hdlSim=[Vivado]
, buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..6]]
}

-- "Unmatchable constant as case subject"
#if MIN_VERSION_clash_lib(1,9,0)
, runTest "XpmCdcPulse" $ def
{ hdlTargets=[VHDL, Verilog]
, hdlLoad=[Vivado]
Expand All @@ -238,8 +221,6 @@ runClashTest = defaultMain $ clashTestRoot
, hdlSim=[Vivado]
, buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
}
#endif

, runTest "DnaPortE2" def
{ hdlTargets=[VHDL, Verilog]
, hdlLoad=[Vivado]
Expand Down Expand Up @@ -305,8 +286,6 @@ runClashTest = defaultMain $ clashTestRoot
]
}
in runTest "Ila" _opts
-- Pattern match failure in 'do' block at /home/peter/src/clash/clash-cores/test-suite/shouldwork/Xilinx/Ila.hs:103:3-8
#if MIN_VERSION_clash_lib(1,9,0)
, let _opts =
def{ hdlTargets=[VHDL, Verilog, SystemVerilog]
, buildTargets=BuildSpecific [ "testWithDefaultsOne"
Expand All @@ -317,7 +296,6 @@ runClashTest = defaultMain $ clashTestRoot
]
}
in outputTest "Ila" _opts
#endif
, outputTest "VIO" def{
hdlTargets=[VHDL]
, buildTargets=BuildSpecific ["withSetName", "withSetNameNoResult"]
Expand Down

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