TLToAXI4 should not block AXI4-b writeacks indefinitely

[jerryz123]

rocket-chip/src/main/scala/tilelink/ToAXI4.scala

Lines 205 to 209 in 025184e

	// R and B => D arbitration
	val r_holds_d = RegInit(Bool(false))
	when (out.r.fire()) { r_holds_d := !out.r.bits.last }
	// Give R higher priority than B
	val r_wins = out.r.valid || r_holds_d

The current arbitration policy in the TLToAXI4 converter always prioritizes AXI4 r-channel responses. This policy leads to starvation for clients waiting for a AccessAck, when the AXI4 r-channel is saturated. For example, a system where the L2 cache evicts a line, then saturates AXI4 with reads, may stall indefinitely waiting for a WriteAck.

This PR implements an alternate policy that stalls for b-channel acks if the b-channel ack has been blocked for 7 consecutive cycles. This is just one possible approach to avoid the indefinite stall.

Type of issue: bug report

Development Phase: implementation

[jerryz123]

@hcook @terpstra

[hcook]

Ideally this would be a configurable policy, but I agree this approach will prevent starvation and so is better than the status quo. What led you to choose the number 7?

[terpstra]

-- deleted --

[terpstra]

I agree a configurable policy would be better, but this is better than nothing.