TraceGen should observe dmem.ordered when attempting a fence #2779
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Related issue:
Previously, the TraceGen unit performed fences by simply waiting for all inflight loads/store to be ack'd. Since this does not perform a microarchitectural fence in the target memory system, the resulting trace can appear to fail memory consistency checks. riscv-boom/riscv-boom#524
The solution is to observe the signal indicating when the target memory system is ready for a fence.
Type of change: bug report
Impact: API modification
Development Phase: implementation
Release Notes