L2TLB never reads after writing

[ingallsj]

Type of change: bug report

Impact: performance improvement, no functional change

Development Phase: implementation

Release Notes
This only affects designs with MMU and clock gating.

The bug is that an L2TLB write will almost always block the next L2TLB search, even many cycles later, because the l2_refill register doesn't clear until the next search enables the clock.

We can break out of this loop if we get lucky, if a request from the other L1TLB will enable the clock with arb.io.out.valid, or a PTW will not allocate the L2TLB (i.e. a superpage or a faulty translation), or an SFENCE will enable the clock with io.dpath.sfence.valid.

The fix is to add the l2_refill register to ptw_clock_en.

customCSRs.disableDCacheClockGate is a work-around to utilize the L2TLB at the cost of extra power.

[aswaterman]

Thanks for the fix!