add several spaces

chipsalliance · May 23, 2023 · c293b4d · c293b4d
1 parent 7de0dd6
commit c293b4d
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/devices/tilelink/MSWI.scala b/src/main/scala/devices/tilelink/MSWI.scala
@@ -133,7 +133,7 @@ object SWI {
     }
 
     val swiRegGroup = RegFieldGroup(mswiType + "sip", Some(mswiType.toUpperCase + "SIP Bits"), ipi.zipWithIndex.flatMap { case (r, i) => 
-      RegField(1, r, RegFieldDesc(mswiType+s"sip_$i", mswiType.toUpperCase+s"SIP bit for Hart $i", reset=Some(0))) :: RegField(SWIConsts.ipiWidth - 1) :: Nil })
+      RegField(1, r, RegFieldDesc(mswiType + s"sip_$i", mswiType.toUpperCase + s"SIP bit for Hart $i", reset=Some(0))) :: RegField(SWIConsts.ipiWidth - 1) :: Nil })
 
     swiRegGroup
   }