Fix unittests

src/main/scala/amba/ahb/Bundles.scala

@@ -50,9 +50,9 @@ class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle
   val hready  = Input(Bool())
 
   // Handy methods that don't care about lite
-  def lock():   Bool = if (params.lite) hmastlock.get else hlock.get
-  def busreq(): Bool = if (params.lite) Wire(true.B) else hbusreq.get
-  def grant():  Bool = if (params.lite) Wire(true.B) else hgrant.get
+  def lock():   Bool = if (params.lite) hmastlock.get    else hlock.get
+  def busreq(): Bool = if (params.lite) WireInit(true.B) else hbusreq.get
+  def grant():  Bool = if (params.lite) WireInit(true.B) else hgrant.get
 
   // A-phase signals from master to arbiter
   val htrans  = Output(UInt(params.transBits.W))

src/main/scala/amba/ahb/SRAM.scala

@@ -34,7 +34,7 @@ class AHBRAM(
 
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) with HasJustOneSeqMem {
-    val (in, _) = node.in(0)
+    val (in, edge) = node.in(0)
     val laneDataBits = 8
     val mem = makeSinglePortedByteWriteSeqMem(
       size = BigInt(1) << mask.filter(b=>b).size,
@@ -67,8 +67,8 @@ class AHBRAM(
 
     // Pending write?
     val p_valid     = RegInit(false.B)
-    val p_address   = Reg(a_address)
-    val p_mask      = Reg(a_mask)
+    val p_address   = Reg(UInt())
+    val p_mask      = Reg(UInt(a_mask.getWidth.W))
     val p_latch_d   = Reg(Bool())
     val p_wdata     = d_wdata holdUnless p_latch_d
 
@@ -100,7 +100,7 @@ class AHBRAM(
                       map { case (m, (p, r)) => Mux(d_bypass && m, p, r) })
 
     // Don't fuzz hready when not in data phase
-    val d_request = Reg(false.B)
+    val d_request = RegInit(false.B)
     when (in.hready) { d_request := false.B }
     when (a_request)  { d_request := true.B }
 

src/main/scala/amba/ahb/Test.scala

@@ -40,6 +40,7 @@ class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
 class AHBNativeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AHBFuzzNative(aFlow, txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }
 
 trait HasFuzzTarget {
@@ -106,4 +107,5 @@ class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
 class AHBBridgeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AHBFuzzBridge(aFlow, txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }

src/main/scala/amba/ahb/ToTL.scala

@@ -66,8 +66,8 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
       val d_pause = RegInit(true.B)
       val d_fail  = RegInit(false.B)
       val d_write = RegInit(false.B)
-      val d_addr  = Reg(in.haddr)
-      val d_size  = Reg(out.a.bits.size)
+      val d_addr  = Reg(UInt(edgeIn.bundle.addrBits.W))
+      val d_size  = Reg(UInt(edgeOut.bundle.sizeBits.W))
       val d_user  = Reg(BundleMap(edgeOut.bundle.requestFields))
 
       when (out.d.valid) { d_recv  := false.B }

src/main/scala/amba/ahb/Xbar.scala

@@ -43,7 +43,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
 
       val (in, _) = node.in(0)
       val a_sel = VecInit(route_addrs.map(seq => seq.map(_.contains(in.haddr)).reduce(_ || _)))
-      val d_sel = Reg(a_sel)
+      val d_sel = RegInit(a_sel)
 
       when (in.hready) { d_sel := a_sel }
       (a_sel zip io_out) foreach { case (sel, out) =>

src/main/scala/amba/apb/Test.scala

@@ -45,4 +45,5 @@ class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
 class APBBridgeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new APBFuzzBridge(aFlow, txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }

src/main/scala/amba/axi4/AsyncCrossing.scala

@@ -132,4 +132,5 @@ class AXI4RAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule
 class AXI4RAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AXI4RAMAsyncCrossing(txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }

src/main/scala/amba/axi4/Delayer.scala

@@ -45,12 +45,18 @@ class AXI4Delayer(q: Double)(implicit p: Parameters) extends LazyModule
       bits.qos   := LFSRNoiseMaker(bits.params.qosBits)
     }
 
-    (node.in zip node.out) foreach { case ((in, _), (out, _)) =>
-      val arnoise = Wire(in.ar.bits)
-      val awnoise = Wire(in.aw.bits)
-      val wnoise  = Wire(in.w .bits)
-      val rnoise  = Wire(in.r .bits)
-      val bnoise  = Wire(in.b .bits)
+    (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
+      val arnoise = Wire(new AXI4BundleAR(edgeIn.bundle))
+      val awnoise = Wire(new AXI4BundleAW(edgeIn.bundle))
+      val wnoise  = Wire(new  AXI4BundleW(edgeIn.bundle))
+      val rnoise  = Wire(new  AXI4BundleR(edgeIn.bundle))
+      val bnoise  = Wire(new  AXI4BundleB(edgeIn.bundle))
+
+      arnoise := DontCare
+      awnoise := DontCare
+      wnoise := DontCare
+      rnoise := DontCare
+      bnoise := DontCare
 
       anoise(arnoise)
       anoise(awnoise)

src/main/scala/amba/axi4/RegisterRouter.scala

@@ -39,17 +39,17 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes
     val fields = AXI4RRIdField(ar.bits.params.idBits) +: ar.bits.params.echoFields
     val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, fields)
     val in = Wire(Decoupled(new RegMapperInput(params)))
-    val ar_extra = WireDefault(in.bits.extra)
-    val aw_extra = WireDefault(in.bits.extra)
+    val ar_extra = Wire(BundleMap(params.extraFields))
+    val aw_extra = Wire(BundleMap(params.extraFields))
 
     // Prefer to execute reads first
     in.valid := ar.valid || (aw.valid && w.valid)
     ar.ready := in.ready
     aw.ready := in.ready && !ar.valid && w .valid
     w .ready := in.ready && !ar.valid && aw.valid
 
-    ar_extra :<= ar.bits.echo
-    aw_extra :<= aw.bits.echo
+    ar_extra.partialAssignL(ar.bits.echo)
+    aw_extra.partialAssignL(aw.bits.echo)
     ar_extra(AXI4RRId) := ar.bits.id
     aw_extra(AXI4RRId) := aw.bits.id
     val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr)

src/main/scala/amba/axi4/Test.scala

@@ -39,6 +39,7 @@ class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
 class AXI4LiteFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AXI4LiteFuzzRAM(txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }
 
 class AXI4LiteUserBitsFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
@@ -62,6 +63,7 @@ class AXI4LiteUserBitsFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyMod
 class AXI4LiteUserBitsFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AXI4LiteUserBitsFuzzRAM(txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }
 
 class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
@@ -85,6 +87,7 @@ class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
 class AXI4FullFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AXI4FullFuzzRAM(txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }
 
 trait HasFuzzTarget {
@@ -158,4 +161,5 @@ class AXI4FuzzBridge(txns: Int)(implicit p: Parameters) extends LazyModule
 class AXI4BridgeTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AXI4FuzzBridge(txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }

src/main/scala/amba/axi4/Xbar.scala

@@ -336,4 +336,5 @@ class AXI4XbarTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Paramete
   val dut12 = Module(LazyModule(new AXI4XbarFuzzTest("Xbar DUT12", txns, 1, 2)).module)
   val dut22 = Module(LazyModule(new AXI4XbarFuzzTest("Xbar DUT22", txns, 2, 2)).module)
   io.finished := Seq(dut21, dut12, dut22).map(_.io.finished).reduce(_ || _)
+  Seq(dut21, dut12, dut22).foreach(_.io.start := io.start)
 }

src/main/scala/devices/tilelink/MasterMux.scala

@@ -63,7 +63,7 @@ class MasterMux(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(impl
     in0.a.ready := !stall && out.a.ready &&  bypass
     in1.a.ready := !stall && out.a.ready && !bypass
     out.a.valid := !stall && Mux(bypass, in0.a.valid, in1.a.valid)
-    def castA(x: TLBundleA) = { val ret = Wire(out.a.bits); ret <> x; ret }
+    def castA(x: TLBundleA) = { val ret = Wire(x.cloneType); ret <> x; ret }
     out.a.bits := Mux(bypass, castA(in0.a.bits), castA(in1.a.bits))
 
     out.d.ready := Mux(bypass, in0.d.ready, in1.d.ready)

src/main/scala/devices/tilelink/TestRAM.scala

@@ -83,4 +83,5 @@ class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) exten
 class TLRAMZeroDelayTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes, txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }

src/main/scala/regmapper/RegisterCrossing.scala

@@ -107,6 +107,7 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
   control.io.master_response_ready := io.master_port.response.ready
   io.master_port.request.ready  := control.io.master_request_ready
   io.master_port.response.valid := control.io.master_response_valid
+  io.master_port.response.bits  := DontCare
 
   control.io.crossing_request_ready := crossing.io.enq.ready
   crossing.io.enq.valid := control.io.crossing_request_valid

src/main/scala/regmapper/Test.scala

@@ -60,10 +60,10 @@ object RRTestCombinational
   }
 
   def combo(bits: Int, rvalid: Bool => Bool, wready: Bool => Bool): RegField = {
-    val combo = Module(new RRTestCombinational(bits, rvalid, wready))
+    lazy val combo = Module(new RRTestCombinational(bits, rvalid, wready))
     RegField(bits,
-      RegReadFn { ready => combo.io.rready := ready; (combo.io.rvalid, combo.io.rdata) },
-      RegWriteFn { (valid, data) => combo.io.wvalid := valid; combo.io.wdata := data; combo.io.wready })
+      RegReadFn(ready => {combo.io.rready := ready; (combo.io.rvalid, combo.io.rdata) }),
+      RegWriteFn((valid, data) => {combo.io.wvalid := valid; combo.io.wdata := data; combo.io.wready }))
   }
 }
 
@@ -232,13 +232,15 @@ abstract class RRTest1(address: BigInt, concurrency: Int, undefZero: Boolean = t
       val field = UInt(bits.W)
 
       val readCross = Module(new RegisterReadCrossing(field))
+      readCross.io := DontCare
       readCross.io.master_clock  := clock
       readCross.io.master_reset  := reset
       readCross.io.master_bypass := false.B
       readCross.io.slave_clock   := clocks.io.clock_out
       readCross.io.slave_reset   := reset
 
       val writeCross = Module(new RegisterWriteCrossing(field))
+      writeCross.io := DontCare
       writeCross.io.master_clock  := clock
       writeCross.io.master_reset  := reset
       writeCross.io.master_bypass := false.B

src/main/scala/tilelink/AsyncCrossing.scala

@@ -150,4 +150,6 @@ class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p
   val dut_wide   = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module)
   val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module)
   io.finished := dut_wide.io.finished && dut_narrow.io.finished
+  dut_wide.io.start := io.start
+  dut_narrow.io.start := io.start
 }

src/main/scala/tilelink/AtomicAutomata.scala

@@ -340,4 +340,5 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule
 class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }

src/main/scala/tilelink/RegisterRouterTest.scala

@@ -31,6 +31,7 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
 class TLRR0Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new FuzzRRTest0(txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }
 
 class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
@@ -48,5 +49,6 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
 class TLRR1Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new FuzzRRTest1(txns)).module)
   io.finished := dut.io.finished
+  dut.io.start := io.start
 }
 

src/main/scala/tilelink/ToAHB.scala

@@ -3,6 +3,7 @@
 package freechips.rocketchip.tilelink
 
 import chisel3._
+import chisel3.util._
 import freechips.rocketchip.amba._
 import freechips.rocketchip.amba.ahb._
 import org.chipsalliance.cde.config.Parameters
@@ -79,6 +80,7 @@ class TLToAHB(val aFlow: Boolean = false, val supportHints: Boolean = true, val
 
       // Initial FSM state
       val resetState = Wire(new AHBControlBundle(edgeIn))
+      resetState := DontCare
       resetState.full  := false.B
       resetState.send  := false.B
       resetState.first := true.B
@@ -205,8 +207,8 @@ class TLToAHB(val aFlow: Boolean = false, val supportHints: Boolean = true, val
       // commited AHB requests (A+D phases = 2). To decouple d_ready from
       // a_ready and htrans, we add another entry for aFlow=false.
       val depth = if (aFlow) 2 else 3
-      val d = Wire(in.d)
-      in.d :<> Queue(d, depth, true)
+      val d = Wire(new DecoupledIO(new TLBundleD(edgeIn.bundle)))
+      in.d :<> Queue(d, depth, flow=true)
       assert (!d.valid || d.ready)
 
       val d_flight = RegInit(0.U(2.W))