Make vLen a CDE param

chipsalliance · Apr 26, 2023 · 2a4526d · 2a4526d
1 parent d9be8ed
commit 2a4526d
Show file tree

Hide file tree

Showing 4 changed files with 16 additions and 7 deletions.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -27,6 +27,7 @@ case class RocketCoreParams(
   useSCIE: Boolean = false,
   useBitManip: Boolean = false,
   useBitManipCrypto: Boolean = false,
+  useVector: Boolean = false,
   useCryptoNIST: Boolean = false,
   useCryptoSM: Boolean = false,
   nLocalInterrupts: Int = 0,

diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -337,6 +337,15 @@ class WithHypervisor(hext: Boolean = true) extends Config((site, here, up) => {
   }
 })
 
+class WithVector(vLen: Int, vext: Boolean = true) extends Config((site, here, up) => {
+  case VLen => vLen
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(useVector = vext)))
+    case t => t
+  }
+})
+
 class WithRoccExample extends Config((site, here, up) => {
   case BuildRoCC => List(
     (p: Parameters) => {

diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
@@ -24,7 +24,7 @@ trait CoreParams {
   val useCompressed: Boolean
   val useBitManip: Boolean
   val useBitManipCrypto: Boolean
-  val useVector: Boolean = true
+  val useVector: Boolean
   val useSCIE: Boolean
   val useCryptoNIST: Boolean
   val useCryptoSM: Boolean
@@ -66,10 +66,8 @@ trait CoreParams {
   def dcacheReqTagBits: Int = 6
 
   def minFLen: Int = 32
-  def vLen: Int = 256
   def sLen: Int = 0
   def eLen(xLen: Int, fLen: Int): Int = xLen max fLen
-  def vMemDataBits: Int = 32
 }
 
 trait HasCoreParameters extends HasTileParameters {
@@ -99,7 +97,7 @@ trait HasCoreParameters extends HasTileParameters {
   val fetchBytes = coreParams.fetchBytes
   val coreInstBits = coreParams.instBits
   val coreInstBytes = coreInstBits/8
-  val coreDataBits = xLen max fLen max vMemDataBits
+  val coreDataBits = xLen max fLen
   val coreDataBytes = coreDataBits/8
   def coreMaxAddrBits = paddrBits max vaddrBitsExtended
 
@@ -112,16 +110,14 @@ trait HasCoreParameters extends HasTileParameters {
   val customIsaExt = coreParams.customIsaExt
   val traceHasWdata = coreParams.traceHasWdata
 
-  def vLen = coreParams.vLen
+  def vLen = p(VLen)
   def sLen = coreParams.sLen
   def eLen = coreParams.eLen(xLen, fLen)
-  def vMemDataBits = if (usingVector) coreParams.vMemDataBits else 0
   def maxVLMax = vLen
 
   if (usingVector) {
     require(isPow2(vLen), s"vLen ($vLen) must be a power of 2")
     require(eLen >= 32 && vLen % eLen == 0, s"eLen must divide vLen ($vLen) and be no less than 32")
-    require(vMemDataBits >= eLen && vLen % vMemDataBits == 0, s"vMemDataBits ($vMemDataBits) must divide vLen ($vLen) and be no less than eLen ($eLen)")
   }
 
   lazy val hartIdLen: Int = p(MaxHartIdBits)

diff --git a/src/main/scala/tile/Vector.scala b/src/main/scala/tile/Vector.scala
@@ -12,6 +12,7 @@ import freechips.rocketchip.rocket._
 import freechips.rocketchip.tilelink._
 
 case object BuildVector extends Field[Option[Parameters => Vector]](None)
+case object VLen extends Field[Int](0)
 
 class VectorCommand(implicit p: Parameters) extends CoreBundle()(p) {
   val inst = Bits(32.W)
@@ -41,6 +42,8 @@ abstract class Vector()(implicit p: Parameters) extends LazyModule {
   val module: VectorModuleImp
   val atlNode: TLNode = TLIdentityNode()
   val tlNode: TLNode = TLIdentityNode()
+
+  require(p(VLen) > 0, s"vLen can not be 0 when instantiating Vector module, do you forget to apply WithVector?")
 }
 
 class VectorModuleImp(outer: Vector) extends LazyModuleImp(outer) {