verification: guard statements with module reset

[ekiwi]

Contributor Checklist

• x Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you add appropriate documentation in docs/src?
• Did you state the API impact?
• Did you specify the code generation impact?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Type of Improvement

• behavior change for consistency

API Impact

• guards the new assert, assume and cover statements with the current default reset

Backend Code Generation Impact

• this will change the Verilog to disable verification statements when reset is active

Desired Merge Strategy

• squash

Release Notes

Assert, assume and cover statements are now disabled during reset by default. If you want your assertion to be active at all times, you can create a reset scope with reset=false.

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels?
• Did you mark the proper milestone (3.2.x, 3.3.x, 3.4.x, 3.5.0) ?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
• Did you mark as Please Merge?

[ekiwi]

Do we treat this as a bug and backport to 3.4.x or do we treat this as a behavioral change (which it is) and only add it to the pre-release branch?

[jackkoenig]

Discussed offline but this is a bug, so we're backporting