SeqUtils asUInt endian-ness: hi/lo instead of right/left

[ingallsj]

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
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• Did you specify the code generation impact?
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Type of Improvement

• backend code generation

API Impact

this changes the Chisel Naming from #1448 to notate endianness as "hi/lo" instead of "right/left", because Scala and Verilog use opposite endianness in lists/arrays

Backend Code Generation Impact

With #1448, this Chisel

val out2 = Seq(signalname(0), signalname(1)).asUInt
val out4 = Seq(signalname(0), signalname(1), signalname(2), signalname(3)).asUInt

would generate this Verilog:

wire [1:0] out2 = {signalname_right, signalname_left};
wire [3:0] out4 = {signalname_right_right, signalname_right_left, signalname_left_right, signalname_left_left};

This looks backwards to me when reading the Verilog: the rights and lefts are reversed. So instead, with this change:

wire [1:0] out2 = {signalname_hi, signalname_lo};
wire [3:0] out4 = {signalname_hi_hi, signalname_hi_lo, signalname_lo_hi, signalname_lo_lo};

Desired Merge Strategy

• Squash: The PR will be squashed and merged (choose this if you have no preference.)

Release Notes

Verilog generation: asUInt endianness "hi/lo" instead of "right/left"

Reviewer Checklist (only modified by reviewer)

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[aswaterman]

Looks better to me.