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Enable Cat of Zero Element Vec (#1623) (#1626)
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* Return 0.U for asUInt of a zero-element Seq

Add a condition to SeqUtils.asUInt to have it return an unspecified
width 0.U when applied to an empty sequence. This enables the ability
to do a Cat of a zero-element sequence.

Signed-off-by: Schuyler Eldridge <[email protected]>

* Test elaboration of Cat on zero-element Seq

Signed-off-by: Schuyler Eldridge <[email protected]>
(cherry picked from commit ac641fb)

Co-authored-by: Schuyler Eldridge <[email protected]>
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mergify[bot] and seldridge authored Oct 19, 2020
1 parent b6b76eb commit f59f391
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Showing 3 changed files with 39 additions and 1 deletion.
5 changes: 4 additions & 1 deletion core/src/main/scala/chisel3/SeqUtils.scala
Original file line number Diff line number Diff line change
Expand Up @@ -16,12 +16,15 @@ private[chisel3] object SeqUtils {
* in the sequence forms the most significant bits.
*
* Equivalent to r(n-1) ## ... ## r(1) ## r(0).
* @note This returns a `0.U` if applied to a zero-element `Vec`.
*/
def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg

/** @group SourceInfoTransformMacros */
def do_asUInt[T <: Bits](in: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = {
if (in.tail.isEmpty) {
if (in.isEmpty) {
0.U
} else if (in.tail.isEmpty) {
in.head.asUInt
} else {
val left = asUInt(in.slice(0, in.length/2))
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1 change: 1 addition & 0 deletions src/main/scala/chisel3/util/Cat.scala
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ object Cat {
* in the sequence forms the least significant bits.
*
* Equivalent to r(0) ## r(1) ## ... ## r(n-1).
* @note This returns a `0.U` if applied to a zero-element `Vec`.
*/
def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse)
}
34 changes: 34 additions & 0 deletions src/test/scala/chiselTests/util/CatSpec.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
// SPDX-License-Identifier: Apache-2.0

package chiselTests.util

import chisel3._
import chisel3.stage.ChiselStage
import chisel3.util.Cat

import chiselTests.ChiselFlatSpec

object CatSpec {

class JackIsATypeSystemGod extends MultiIOModule {
val in = IO(Input (Vec(0, UInt(8.W))))
val out = IO(Output(UInt(8.W)))

out := Cat(in)
}

}

class CatSpec extends ChiselFlatSpec {

import CatSpec._

behavior of "util.Cat"

it should "not fail to elaborate a zero-element Vec" in {

ChiselStage.elaborate(new JackIsATypeSystemGod)

}

}

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