Make it legal for concrete resets to drive abstract reset (backport #…

…2018) (#2029) * Make it legal for concrete resets to drive abstract reset (#2018) This has been legal in FIRRTL since v1.2.3 (when reset inference started using a unification-style algorithm) but was never exposed in the Chisel API. Also delete the overridden connects in AsyncReset and ResetType which just duplicate logic from MonoConnect. (cherry picked from commit 4b7b771) * Fix issues with tests Co-authored-by: Jack Koenig <[email protected]>
chipsalliance · Jul 9, 2021 · 8bcdfda · 8bcdfda
1 parent 1153de8
commit 8bcdfda
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Showing 3 changed files with 17 additions and 10 deletions.
diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala
@@ -987,11 +987,6 @@ final class ResetType(private[chisel3] val width: Width = Width(1)) extends Elem
   private[chisel3] def typeEquivalent(that: Data): Boolean =
     this.getClass == that.getClass
 
-  override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match {
-    case _: Reset | DontCare => super.connect(that)(sourceInfo, connectCompileOptions)
-    case _ => super.badConnect(that)(sourceInfo)
-  }
-
   override def litOption = None
 
   /** Not really supported */
@@ -1034,11 +1029,6 @@ sealed class AsyncReset(private[chisel3] val width: Width = Width(1)) extends El
   private[chisel3] def typeEquivalent(that: Data): Boolean =
     this.getClass == that.getClass
 
-  override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match {
-    case _: AsyncReset | DontCare => super.connect(that)(sourceInfo, connectCompileOptions)
-    case _ => super.badConnect(that)(sourceInfo)
-  }
-
   override def litOption = None
 
   /** Not really supported */

diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala
@@ -103,6 +103,8 @@ private[chisel3] object MonoConnect {
         elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
       case (sink_e: ResetType, source_e: Reset) =>
         elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+      case (sink_e: Reset, source_e: ResetType) =>
+        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
       case (sink_e: EnumType, source_e: UnsafeEnum) =>
         elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
       case (sink_e: EnumType, source_e: EnumType) if sink_e.typeEquivalent(source_e) =>

diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
@@ -35,6 +35,13 @@ class AbstractResetDontCareModule extends RawModule {
   bulkAggPort <> DontCare
 }
 
+class ResetDriveConcrete(tpe: Reset) extends RawModule {
+  val in = IO(Input(tpe))
+  val out = IO(Output(tpe))
+  val w = Wire(Reset())
+  w := in
+  out := w
+}
 
 class ResetSpec extends ChiselFlatSpec with Utils {
 
@@ -44,6 +51,14 @@ class ResetSpec extends ChiselFlatSpec with Utils {
     ChiselStage.elaborate(new AbstractResetDontCareModule)
   }
 
+  it should "be able to drive Bool" in {
+    compile(new ResetDriveConcrete(Bool()))
+  }
+
+  it should "be able to drive AsyncReset" in {
+    compile(new ResetDriveConcrete(AsyncReset()))
+  }
+
   it should "allow writing modules that are reset agnostic" in {
     val sync = compile(new Module {
       val io = IO(new Bundle {