Rename MultiIOModule to Module

core/src/main/scala/chisel3/Annotation.scala

@@ -4,7 +4,7 @@ package chisel3.experimental
 
 import scala.language.existentials
 import chisel3.internal.{Builder, InstanceId, LegacyModule}
-import chisel3.{CompileOptions, Data}
+import chisel3.{CompileOptions, Data, RawModule}
 import firrtl.Transform
 import firrtl.annotations._
 import firrtl.options.Unserializable
@@ -78,7 +78,7 @@ object doNotDedup {
     * @param module The module to be marked
     * @return Unmodified signal `module`
     */
-   def apply[T <: LegacyModule](module: T)(implicit compileOptions: CompileOptions): Unit = {
+   def apply[T <: RawModule](module: T)(implicit compileOptions: CompileOptions): Unit = {
     annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) })
   }
 }

core/src/main/scala/chisel3/Module.scala

@@ -6,15 +6,14 @@ import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 import scala.collection.JavaConversions._
 import scala.language.experimental.macros
-
 import java.util.IdentityHashMap
 
 import chisel3.internal._
 import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
-import chisel3.internal.sourceinfo.{InstTransform, SourceInfo}
+import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
 import chisel3.experimental.BaseModule
-import _root_.firrtl.annotations.{ModuleName, ModuleTarget, IsModule}
+import _root_.firrtl.annotations.{IsModule, ModuleName, ModuleTarget}
 
 object Module extends SourceInfoDoc {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -87,6 +86,43 @@ object Module extends SourceInfoDoc {
   def currentModule: Option[BaseModule] = Builder.currentModule
 }
 
+/** Abstract base class for Modules, which behave much like Verilog modules.
+  * These may contain both logic and state which are written in the Module
+  * body (constructor).
+  * This abstract base class includes an implicit clock and reset.
+  *
+  * @note Module instantiations must be wrapped in a Module() call.
+  */
+abstract class Module(implicit moduleCompileOptions: CompileOptions) extends RawModule {
+  // Implicit clock and reset pins
+  final val clock: Clock = IO(Input(Clock())).suggestName("clock")
+  final val reset: Reset = IO(Input(mkReset)).suggestName("reset")
+
+  // These are to be phased out
+  protected var override_clock: Option[Clock] = None
+  protected var override_reset: Option[Bool] = None
+
+  private[chisel3] def mkReset: Reset = {
+    // Top module and compatibility mode use Bool for reset
+    val inferReset = _parent.isDefined && moduleCompileOptions.inferModuleReset
+    if (inferReset) Reset() else Bool()
+  }
+
+  // Setup ClockAndReset
+  Builder.currentClock = Some(clock)
+  Builder.currentReset = Some(reset)
+  Builder.clearPrefix()
+
+  private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
+    implicit val sourceInfo = UnlocatableSourceInfo
+
+    super.initializeInParent(parentCompileOptions)
+    clock := override_clock.getOrElse(Builder.forcedClock)
+    reset := override_reset.getOrElse(Builder.forcedReset)
+  }
+}
+
+
 package experimental {
 
   object IO {
@@ -145,7 +181,7 @@ package internal {
       if (!compileOptions.explicitInvalidate) {
         pushCommand(DefInvalid(sourceInfo, clonePorts.ref))
       }
-      if (proto.isInstanceOf[MultiIOModule]) {
+      if (proto.isInstanceOf[Module]) {
         clonePorts("clock") := Module.clock
         clonePorts("reset") := Module.reset
       }

core/src/main/scala/chisel3/RawModule.scala

@@ -142,47 +142,14 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
   }
 }
 
-trait RequireAsyncReset extends MultiIOModule {
+trait RequireAsyncReset extends Module {
   override private[chisel3] def mkReset: AsyncReset = AsyncReset()
 }
 
-trait RequireSyncReset extends MultiIOModule {
+trait RequireSyncReset extends Module {
   override private[chisel3] def mkReset: Bool = Bool()
 }
 
-/** Abstract base class for Modules, which behave much like Verilog modules.
-  * These may contain both logic and state which are written in the Module
-  * body (constructor).
-  * This abstract base class includes an implicit clock and reset.
-  *
-  * @note Module instantiations must be wrapped in a Module() call.
-  */
-abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions)
-    extends RawModule {
-  // Implicit clock and reset pins
-  final val clock: Clock = IO(Input(Clock())).autoSeed("clock")
-  final val reset: Reset = IO(Input(mkReset)).autoSeed("reset")
-
-  private[chisel3] def mkReset: Reset = {
-    // Top module and compatibility mode use Bool for reset
-    val inferReset = _parent.isDefined && moduleCompileOptions.inferModuleReset
-    if (inferReset) Reset() else Bool()
-  }
-
-  // Setup ClockAndReset
-  Builder.currentClock = Some(clock)
-  Builder.currentReset = Some(reset)
-  Builder.clearPrefix()
-
-  private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
-    implicit val sourceInfo = UnlocatableSourceInfo
-
-    super.initializeInParent(parentCompileOptions)
-    clock := Builder.forcedClock
-    reset := Builder.forcedReset
-  }
-}
-
 package internal {
 
   /** Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor
@@ -192,12 +159,7 @@ package internal {
     * IO), the clock and reset constructors will be phased out. Recommendation is to wrap the module
     * in a withClock/withReset/withClockAndReset block, or directly hook up clock or reset IO pins.
     */
-  abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
-    extends MultiIOModule {
-    // These are to be phased out
-    protected var override_clock: Option[Clock] = None
-    protected var override_reset: Option[Bool] = None
-
+  abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) extends Module {
     // IO for this Module. At the Scala level (pre-FIRRTL transformations),
     // connections in and out of a Module may only go through `io` elements.
     @deprecated("Removed for causing issues in Scala 2.12+. You remain free to define io Bundles " +
@@ -233,18 +195,5 @@ package internal {
 
       super.generateComponent()
     }
-
-    private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
-      // Don't generate source info referencing parents inside a module, since this interferes with
-      // module de-duplication in FIRRTL emission.
-      implicit val sourceInfo = UnlocatableSourceInfo
-
-      if (!parentCompileOptions.explicitInvalidate) {
-        pushCommand(DefInvalid(sourceInfo, _io.ref))
-      }
-
-      clock := override_clock.getOrElse(Builder.forcedClock)
-      reset := override_reset.getOrElse(Builder.forcedReset)
-    }
   }
 }

core/src/main/scala/chisel3/core/package.scala

@@ -66,13 +66,13 @@ package object core {
   type RawModule = chisel3.RawModule
   @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " +
     "Use chisel3.MultiIOModule instead. This alias will be removed in 3.4.", "since the beginning of time")
-  type MultiIOModule = chisel3.MultiIOModule
+  type MultiIOModule = chisel3.Module
   @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " +
     " Use chisel3.RawModule instead. This alias will be removed in 3.4.", "since the beginning of time")
   type UserModule = chisel3.RawModule
   @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " +
     "Use chisel3.MultiIOModule instead. This alias will be removed in 3.4.", "since the beginning of time")
-  type ImplicitModule = chisel3.MultiIOModule
+  type ImplicitModule = chisel3.Module
 
   @deprecated("Use the version in chisel3._", "3.2")
   val Bits = chisel3.Bits

core/src/main/scala/chisel3/package.scala

@@ -167,7 +167,8 @@ package object chisel3 {
 
   type InstanceId = internal.InstanceId
 
-  type Module = chisel3.internal.LegacyModule
+  @deprecated("MultiIOModule is now just Module", "Chisel 3.5")
+  type MultiIOModule = chisel3.Module
 
   /** Implicit for custom Printable string interpolator */
   implicit class PrintableHelper(val sc: StringContext) extends AnyVal {

src/main/scala/chisel3/aop/injecting/InjectingAspect.scala

@@ -2,7 +2,7 @@
 
 package chisel3.aop.injecting
 
-import chisel3.{Module, ModuleAspect, MultiIOModule, RawModule, experimental, withClockAndReset}
+import chisel3.{Module, ModuleAspect, RawModule, withClockAndReset}
 import chisel3.aop._
 import chisel3.internal.{Builder, DynamicContext}
 import chisel3.internal.firrtl.DefModule
@@ -63,7 +63,7 @@ abstract class InjectorAspect[T <: RawModule, M <: RawModule](
     RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module =>
       val (chiselIR, _) = Builder.build(Module(new ModuleAspect(module) {
         module match {
-          case x: MultiIOModule => withClockAndReset(x.clock, x.reset) { injection(module) }
+          case x: Module => withClockAndReset(x.clock, x.reset) { injection(module) }
           case x: RawModule => injection(module)
         }
       }), dynamicContext)

src/main/scala/chisel3/util/Decoupled.scala

@@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle
 {
   // Compatibility hack for rocket-chip
   private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match {
-    case (true, Some(module: MultiIOModule))
+    case (true, Some(module: Module))
         if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
     case _ => gen
   }

src/test/scala/chiselTests/AnalogIntegrationSpec.scala

@@ -31,15 +31,19 @@ class AnalogBlackBox(index: Int) extends BlackBox(Map("index" -> index)) {
   val io = IO(new AnalogBlackBoxIO(1))
 }
 
+trait AnalogBlackBoxModuleIntf extends Module {
+  def io: AnalogBlackBoxIO
+}
+
 // AnalogBlackBox wrapper, which extends Module to present the common io._ interface
-class AnalogBlackBoxModule(index: Int) extends Module {
+class AnalogBlackBoxModule(index: Int) extends AnalogBlackBoxModuleIntf {
   val io = IO(new AnalogBlackBoxIO(1))
   val impl = Module(new AnalogBlackBox(index))
   io <> impl.io
 }
 
 // Wraps up n blackboxes, connecing their buses and simply forwarding their ports up
-class AnalogBlackBoxWrapper(n: Int, idxs: Seq[Int]) extends Module {
+class AnalogBlackBoxWrapper(n: Int, idxs: Seq[Int]) extends AnalogBlackBoxModuleIntf {
   require(n > 0)
   val io = IO(new AnalogBlackBoxIO(n))
   val bbs = idxs.map(i => Module(new AnalogBlackBoxModule(i)))

src/test/scala/chiselTests/AutoClonetypeSpec.scala

@@ -198,7 +198,7 @@ class AutoClonetypeSpec extends ChiselFlatSpec with Utils {
   }
 
   "Wrapped IO construction without parent reference" should "not fail for autoclonetype" in {
-    class TestModule extends MultiIOModule {
+    class TestModule extends Module {
       def thunk[T](f: => T): T = f
       val works = thunk(IO(new Bundle {
         val x = Output(UInt(3.W))
@@ -208,7 +208,7 @@ class AutoClonetypeSpec extends ChiselFlatSpec with Utils {
   }
 
   "Wrapped IO construction with parent references" should "not fail for autoclonetype" in {
-    class TestModule(blah: Int) extends MultiIOModule {
+    class TestModule(blah: Int) extends Module {
       // Note that this currently fails only if f: =>T on Scala 2.11.12
       // This works successfully with 2.12.11
       def thunk[T](f: => T): T = f

src/test/scala/chiselTests/BoringUtilsSpec.scala

@@ -71,7 +71,7 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
     out := x
   }
 
-  class Top(val width: Int) extends MultiIOModule {
+  class Top(val width: Int) extends Module {
     /* From the perspective of deduplication, all sources are identical and all sinks are identical. */
     val sources = Seq.fill(3)(Module(new Source))
     val sinks = Seq.fill(6)(Module(new Sink))

src/test/scala/chiselTests/CloneModuleSpec.scala

@@ -8,7 +8,7 @@ import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil}
 import chisel3.experimental.{CloneModuleAsRecord, IO}
 import chisel3.testers.BasicTester
 
-class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends MultiIOModule {
+class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends Module {
   val clk = IO(Input(Clock()))
   val rst = IO(Input(Reset()))
   val enq = IO(Flipped(EnqIO(gen)))

src/test/scala/chiselTests/DataPrint.scala

@@ -34,7 +34,7 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
     } }
   }
 
-  class BoundDataModule extends MultiIOModule {  // not in the test to avoid anon naming suffixes
+  class BoundDataModule extends Module {  // not in the test to avoid anon naming suffixes
     Wire(UInt()).toString should be("UInt(Wire in BoundDataModule)")
     Reg(SInt()).toString should be("SInt(Reg in BoundDataModule)")
     val io = IO(Output(Bool()))  // needs a name so elaboration doesn't fail
@@ -44,7 +44,7 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
     (2.U + 2.U).toString should be("UInt<2>(OpResult in BoundDataModule)")
     Wire(Vec(3, UInt(2.W))).toString should be ("UInt<2>[3](Wire in BoundDataModule)")
 
-    class InnerModule extends MultiIOModule {
+    class InnerModule extends Module {
       val io = IO(Output(new Bundle {
         val a = UInt(4.W)
       }))

src/test/scala/chiselTests/Direction.scala

@@ -131,7 +131,7 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
   import chisel3.experimental.{DataMirror, Direction}
 
   property("Directions should be preserved through cloning and binding of Bundles") {
-    ChiselStage.elaborate(new MultiIOModule {
+    ChiselStage.elaborate(new Module {
       class MyBundle extends Bundle {
         val foo = Input(UInt(8.W))
         val bar = Output(UInt(8.W))
@@ -164,11 +164,11 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
       for ((data, dir) <- actualDirs) {
         DataMirror.directionOf(data) shouldBe (dir)
       }
-    }.asInstanceOf[MultiIOModule]) // The cast works around weird reflection behavior (bug?)
+    }.asInstanceOf[Module]) // The cast works around weird reflection behavior (bug?)
   }
 
   property("Directions should be preserved through cloning and binding of Vecs") {
-    ChiselStage.elaborate(new MultiIOModule {
+    ChiselStage.elaborate(new Module {
       val a = Vec(1, Input(UInt(8.W)))
       val b = Vec(1, a)
       val c = Vec(1, Flipped(a))
@@ -197,7 +197,7 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
       for ((data, dir) <- actualDirs) {
         DataMirror.directionOf(data) shouldBe (dir)
       }
-    }.asInstanceOf[MultiIOModule]) // The cast works around weird reflection behavior (bug?)
+    }.asInstanceOf[Module]) // The cast works around weird reflection behavior (bug?)
   }
 
   property("Using Vec and Flipped together should calculate directions properly") {

src/test/scala/chiselTests/DriverSpec.scala

@@ -19,7 +19,7 @@ class DummyModule extends Module {
   io.out := io.in
 }
 
-class TypeErrorModule extends chisel3.MultiIOModule {
+class TypeErrorModule extends chisel3.Module {
   val in = IO(Input(UInt(1.W)))
   val out = IO(Output(SInt(1.W)))
   out := in

src/test/scala/chiselTests/Module.scala

@@ -143,7 +143,7 @@ class ModuleSpec extends ChiselPropSpec with Utils {
   property("DataMirror.modulePorts should work") {
     ChiselStage.elaborate(new Module {
       val io = IO(new Bundle { })
-      val m = Module(new chisel3.MultiIOModule {
+      val m = Module(new chisel3.Module {
         val a = IO(UInt(8.W))
         val b = IO(Bool())
       })

src/test/scala/chiselTests/MultiIOModule.scala

@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 
-class MultiIOPlusOne extends MultiIOModule {
+class MultiIOPlusOne extends Module {
   val in  = IO(Input(UInt(32.W)))
   val out = IO(Output(UInt(32.W)))
 
@@ -20,20 +20,20 @@ class MultiIOTester extends BasicTester {
 }
 
 // Demonstrate multiple IOs with inheritance where the IO is assigned to internally
-trait LiteralOutputTrait extends MultiIOModule {
+trait LiteralOutputTrait extends Module {
   val myLiteralIO = IO(Output(UInt(32.W)))
   myLiteralIO := 2.U
 }
 
 // Demonstrate multiple IOs with inheritance where the IO is not assigned
 // (and must be assigned by what extends this trait).
-trait MultiIOTrait extends MultiIOModule {
+trait MultiIOTrait extends Module {
   val myTraitIO = IO(Output(UInt(32.W)))
 }
 
 // Composition of the two above traits, example of IO composition directly using multiple top-level
 // IOs rather than indirectly by constraining the type of the single .io field.
-class ComposedMultiIOModule extends MultiIOModule
+class ComposedMultiIOModule extends Module
     with LiteralOutputTrait with MultiIOTrait {
   val topModuleIO = IO(Input(UInt(32.W)))
   myTraitIO := topModuleIO

src/test/scala/chiselTests/NamingAnnotationTest.scala

@@ -9,7 +9,7 @@ import chisel3.stage.ChiselStage
 
 import scala.collection.mutable.ListBuffer
 
-trait NamedModuleTester extends MultiIOModule {
+trait NamedModuleTester extends Module {
   val expectedNameMap = ListBuffer[(InstanceId, String)]()
   val expectedModuleNameMap = ListBuffer[(Module, String)]()