hw-model-verilator: Set SRAM to random PUF state on start. #682
fpga.yml
on: pull_request
check_cache
13s
build_test_binaries
4m 47s
cache_fpga_bitstream_artifact
0s
test_artifacts
4m 42s
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caliptra-fpga-bitstream
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18.4 MB |
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caliptra-fpga-kmod
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607 KB |
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caliptra-test-binaries
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114 MB |
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caliptra-test-firmware
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4.84 MB |
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