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Fix #2233 #2267

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merged 2 commits into from
Feb 15, 2024
Merged

Fix #2233 #2267

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3d72a0a
Fix #2233
Rot127 Feb 5, 2024
a498f60
Ensure that a group is never added twice.
Rot127 Feb 6, 2024
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6 changes: 6 additions & 0 deletions Mapping.c
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Original file line number Diff line number Diff line change
Expand Up @@ -181,6 +181,7 @@ void map_implicit_writes(MCInst *MI, const insn_map *imap)
}

/// Adds a given group to @MI->flat_insn.
/// A group is never added twice.
void add_group(MCInst *MI, unsigned /* arch_group */ group)
{
#ifndef CAPSTONE_DIET
Expand All @@ -192,6 +193,11 @@ void add_group(MCInst *MI, unsigned /* arch_group */ group)
printf("ERROR: Too many groups defined.\n");
return;
}
for (int i = 0; i < detail->groups_count; ++i) {
if (detail->groups[i] == group) {
return;
}
}
detail->groups[detail->groups_count++] = group;
#endif // CAPSTONE_DIET
}
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15 changes: 15 additions & 0 deletions arch/ARM/ARMMapping.c
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Expand Up @@ -175,12 +175,27 @@ static void check_pop_return(MCInst *MI) {
}
}

/// Check if PC is directly written.Those instructions
/// are considered of group BRANCH.
static void check_writes_to_pc(MCInst *MI) {
if (!MI->flat_insn->detail)
return;
for (size_t i = 0; i < ARM_get_detail(MI)->op_count; ++i) {
cs_arm_op *op = &ARM_get_detail(MI)->operands[i];
if (op->type == ARM_OP_REG && op->reg == ARM_REG_PC && (op->access & CS_AC_WRITE)) {
add_group(MI, ARM_GRP_JUMP);
return;
}
}
}

/// Adds group to the instruction which are not defined in LLVM.
static void ARM_add_cs_groups(MCInst *MI)
{
if (!MI->flat_insn->detail)
return;
check_pop_return(MI);
check_writes_to_pc(MI);
unsigned Opcode = MI->flat_insn->id;
switch (Opcode) {
default:
Expand Down
7 changes: 5 additions & 2 deletions suite/cstest/issues.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -753,7 +753,7 @@

!# issue 760
!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: WRITE ; Write-back: True ; Registers read: r13 ; Registers modified: r13 r1 r15 ; Groups: IsARM return
0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: WRITE ; Write-back: True ; Registers read: r13 ; Registers modified: r13 r1 r15 ; Groups: IsARM return jump

!# issue 750
!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
Expand All @@ -773,7 +773,7 @@

!# issue 744
!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: WRITE ; Write-back: True ; Registers read: r13 ; Registers modified: r13 r1 r15 ; Groups: IsARM return
0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: WRITE ; Write-back: True ; Registers read: r13 ; Registers modified: r13 r1 r15 ; Groups: IsARM return jump

!# issue 741
!# CS_ARCH_X86, CS_MODE_32, None
Expand Down Expand Up @@ -1047,3 +1047,6 @@
!# CS_ARCH_AARCH64, CS_MODE_ARM, None
0x0: 0x00,0x00,0x00,0x4c == st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]

!# issue 2233 ARM write to PC is branch
!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
0x87,0x46 == mov pc, r0 ; Groups: IsThumb jump
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