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Can Selcik edited this page Mar 25, 2018 · 2 revisions

The device features an ARM SoC from the i.MX6 family by Freescale (--> NXP --> Qualcomm) alongside a Parade TrueTouch Gen5 multitouch screen. The EPaper Display seems to be referred to as es103cs1. The firmware for this display can be found at kernel-mxc-epdc-fb-reference/epdc_ES103CS1.fw. Keep in mind that firmware for EInk displays are not code but simply an array of waveforms.

      epdc@020f4000 {
        compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
        reg = <0x20f4000 0x4000>;
        interrupts = <0x0 0x61 0x4>;
        clocks = <0x2 0x70 0x2 0x73>;
        clock-names = "epdc_axi", "epdc_pix";
        pinctrl-names = "default";
        pinctrl-0 = <0x10>;
        VCOM-supply = <0x11>;
        DISPLAY-supply = <0x12>;
        TMST-supply = <0x13>;
        status = "okay";
      };

remarkable: ~/ cat /proc/device-tree/model
reMarkable Prototype 1

remarkable: ~/ cat /proc/device-tree/compatible 
remarkable,zero-gravitasfsl,imx6sl

remarkable: ~/ cat /proc/bus/input/devices 
I: Bus=0018 Vendor=056a Product=0000 Version=0036
N: Name="Wacom I2C Digitizer"
P: Phys=
S: Sysfs=/devices/soc0/soc/2100000.aips-bus/21a4000.i2c/i2c-1/1-0009/input/input0
U: Uniq=
H: Handlers=mouse0 event0 
B: PROP=0
B: EV=b
B: KEY=1c03 0 0 0 0 0 0 0 0 0 0
B: ABS=f000003

I: Bus=0000 Vendor=0000 Product=0000 Version=0000
N: Name="cyttsp5_mt"
P: Phys=2-0024/input0
S: Sysfs=/devices/soc0/soc/2100000.aips-bus/21a8000.i2c/i2c-2/2-0024/input/input1
U: Uniq=
H: Handlers=event1 
B: PROP=2
B: EV=f
B: KEY=0
B: REL=0
B: ABS=6f38000 2000000

I: Bus=0019 Vendor=0001 Product=0001 Version=0100
N: Name="gpio-keys"
P: Phys=gpio-keys/input0
S: Sysfs=/devices/soc0/gpio-keys/input/input2
U: Uniq=
H: Handlers=kbd event2 
B: PROP=0
B: EV=3
B: KEY=8000 100640 0 0 0

Here is what the EPD controller looks like: EPDC

  • TFT resolutions up to 4096 x 4096 pixels with 20 Hz refresh (programmable up to 8191 x 8191)
  • TFT resolutions up to 1650 x 2332 pixels at 106 Hz refresh (3.8 Mpixel)
  • Industry standard bus interfaces (AMBA AXI and APB)
  • Up to 5-bit pixel representation for up to 32 grayscale levels
  • Up to 64 concurrent updates with partial update support, except for 32(5-bit) gray level panel for which only 16 concurrent updates can be used
  • Automatic collision handling when used in conjunction with the i.MX device driver
  • Dual-scan TFT drive mode to support ultra high resolution/refresh rate displays
  • Flexible direct drive TFT interface supporting next generation source driver, gate driver and panel -architectures, including LVDS, DDR and multi-level source drivers
  • Unified generic configurable timing mode (Pigeon Mode) available on most panel timing control signals
  • High performance pixel pipeline architecture to guarantee refresh performance at high pixel rates without the need for high internal clocking
  • Ability to process multiple updates asynchronously to refresh/update operations with ability to intercept each frame scan will multiple update requests
  • Performance tuning capabilities which can interface with SoC level memory arbitration mechanisms further guaranteeing frame refresh operation
  • Decoupled clocking architecture allowing for independent and asynchronous clock sources for memory bus, peripheral bus and pixel clock domains
  • Full and partial update mode support
  • Support for up to 256 waveform modes, also support optimal waveform autoselection based on gray level of the pixels being updated
  • Low power mode operation via architectural clock gating
  • Update buffer analysis functions to get information like collision rectangle, gray level
  • The latest IMX7 processor supports Regal technology to minimize the need for a full refresh.
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