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std-bit-slice #497 #1903

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14 changes: 14 additions & 0 deletions docs/libraries/core.md
Original file line number Diff line number Diff line change
Expand Up @@ -120,6 +120,20 @@ Slice out the lower OUT_WIDTH bits of an IN_WIDTH-bit value. Computes

---

### `std_bit_slice<IN_WIDTH, START_IDX, END_IDX, OUT_WIDTH>`
Extract the bit-string starting at `START_IDX` and ending at `END_IDX - 1` from `in`.
This is computed as `in[END_IDX:START_IDX]`.`OUT_WIDTH` must be specified to
be `END_WIDTH - START_WITH` wide when instantiating the module.


**Inputs:**
- `in: IN_WIDTH` - An IN_WIDTH-bit value

**Outputs:**

- `out: OUT_WIDTH` - The value of the bit-string `in[START_IDX:END_IDX]`
---

### `std_pad<IN_WIDTH, OUT_WIDTH>`

Given an IN_WIDTH-bit input, zero pad from the left to an output of
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8 changes: 8 additions & 0 deletions examples/tutorial/language-tutorial-bit-slice.expect
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@@ -0,0 +1,8 @@
{
"cycles": 1,
"memories": {
"mem": [
9
]
}
}
27 changes: 27 additions & 0 deletions examples/tutorial/language-tutorial-bit-slice.futil
Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
import "primitives/core.futil";

component main(@go go: 1) -> (@done done: 1) {
cells {
@external mem = std_mem_d1(32, 1, 1);
slice = std_bit_slice(32, 14, 10, 4);
pad = std_pad(4, 32);
}

wires {
group bit_slice {
slice.in = 32'd206256;

pad.in = slice.out;

mem.addr0 = 1'b0;
mem.write_data = pad.out;
mem.write_en = 1'b1;

bit_slice[done] = mem.done;
}
}

control {
bit_slice;
}
}
1 change: 1 addition & 0 deletions primitives/core.futil
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ extern "core.sv" {
comb primitive std_slice<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
comb primitive std_pad<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
comb primitive std_cat<"share"=1>[LEFT_WIDTH, RIGHT_WIDTH, OUT_WIDTH](@data left: LEFT_WIDTH, @data right: RIGHT_WIDTH) -> (out: OUT_WIDTH);
comb primitive std_bit_slice<"share"=1>[IN_WIDTH, START_IDX, END_IDX, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);

/// Logical operators
comb primitive std_not<"share"=1>[WIDTH](@data in: WIDTH) -> (out: WIDTH);
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25 changes: 25 additions & 0 deletions primitives/core.sv
Original file line number Diff line number Diff line change
Expand Up @@ -456,3 +456,28 @@ module std_mem_d4 #(
endmodule

`default_nettype wire

module std_bit_slice #(
parameter IN_WIDTH = 32,
parameter START_IDX = 0,
parameter END_IDX = 31,
parameter OUT_WIDTH = 32
)(
input wire logic [IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[END_IDX:START_IDX];

`ifdef VERILATOR
always_comb begin
if (START_IDX < 0 || END_IDX > IN_WIDTH-1)
$error(
"std_bit_slice: Slice range out of bounds\n",
"IN_WIDTH: %0d", IN_WIDTH,
"START_IDX: %0d", START_IDX,
"END_IDX: %0d", END_IDX,
);
end
`endif

endmodule
5 changes: 5 additions & 0 deletions tests/correctness/std_bit_slice.expect
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
{
"mem": [
9
]
}
27 changes: 27 additions & 0 deletions tests/correctness/std_bit_slice.futil
Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
import "primitives/core.futil";

component main(@go go: 1) -> (@done done: 1) {
cells {
@external mem = std_mem_d1(32, 1, 1);
slice = std_bit_slice(32, 10, 14, 4);
pad = std_pad(4, 32);
}

wires {
group bit_slice {
slice.in = 32'd206256;

pad.in = slice.out;

mem.addr0 = 1'b0;
mem.write_data = pad.out;
mem.write_en = 1'b1;

bit_slice[done] = mem.done;
}
}

control {
bit_slice;
}
}
10 changes: 10 additions & 0 deletions tests/correctness/std_bit_slice.futil.data
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
{
"mem": {
"data": [10],
"format": {
"numeric_type": "bitnum",
"is_signed": false,
"width": 32
}
}
}