[Calyx-Firrtl] Fix undefined values bug by initializing to zero #1841
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I ran into a problem with my FIRRTL backend where both the FIRRTL compiler and ESSENT would squash (for lack of a better term) guarded assignments into a straightforward assignments. For example, the FIRRTL code:
was compiled to the below Verilog:
since there were no other assignments to
done
in the FIRRTL program. This caused the execution to finish in 0 cycles sincedone
was always1
.So, I fixed my backend to insert an assignment to 0, so it would produce the below FIRRTL:
This solves the problem, as the FIRRTL compiler now produces the below Verilog:
and the intended output was produced.
Please let me know if I should fix anything/deal with things more elegantly! (I only changed 2 lines of Rust in this PR 😅 )