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Building...
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67 followers · 91 following
  • Siemens DISW
  • Maadi, Cairo, Egypt
  • 19:06 (UTC +02:00)
  • LinkedIn in/bytesiz3d

Achievements

Achievement: StarstruckAchievement: Pair Extraordinairex3Achievement: YOLOAchievement: Pull Sharkx3Achievement: QuickdrawAchievement: Arctic Code Vault Contributor

Achievements

Achievement: StarstruckAchievement: Pair Extraordinairex3Achievement: YOLOAchievement: Pull Sharkx3Achievement: QuickdrawAchievement: Arctic Code Vault Contributor

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bytesiz3d/README.md

Welcome!

About me

I'm Abdelrahman Farid, an aspiring Computer Engineer. I'm based in Cairo, Egypt. I graduated from Cairo University – Faculty of Engineering, with a BSc. in Computer Engineering in July 2022.

I like Cinema, Photography, and Chess. I'm highly competitive, and I attribute most of my success to my insatiable desire to improve. I'm always looking forward to working on exciting and challenging projects.

Reach me @

Abdelrahman Farid | email bytesiz3d | Linkedin

What I do

Windows linux CPP python golang



I love working on Computer Graphics, Infrastructure, and Systems Programming. I wish to communicate my passion for computers with people through my work.

Resume

🔗📝 PDF Abdelrahman Farid-1

Pinned Loading

  1. json-explorer json-explorer Public

    Cross-platform JSON explorer for your desktop

    C

  2. toy-compiler toy-compiler Public

    Forked from 7asebat/S22-Compilers

    A compiler for a toy Turing-complete programming language. The compiler emits Quadruples and shows the Symbol Table on compilation.

    C++

  3. OS_Scheduler OS_Scheduler Public

    Forked from 7asebat/OS_Scheduler

    C

  4. Smart-Wallet-System Smart-Wallet-System Public

    Smart wallet system simulation (C++/ImGUI/TCP/Linux)

    C++

  5. Pipelined-Processor Pipelined-Processor Public

    Forked from 7asebat/Pipelined-Processor

    An implementation of a PDP-11/MIPS pipelined hybrid in VHDL.

    VHDL

  6. DCNN-Accelerator-FC DCNN-Accelerator-FC Public

    Forked from 7asebat/DCNN-Accelerator-FC

    The fully-connected layer for an Image Processing ASIC.

    Verilog