pulley: Move fp/lr out of XReg set (#9806)

* pulley: Move `fp`/`lr` out of `XReg` set

This commit moves the `fp` and `lr` registers out of the `XReg` register
set and into the `MachineState` per-VM. These are automatically modified
and read with `push_frame` and `pop_frame`. Dedicated `xmov_{fp,lr}`
instructions were added for use in Wasmtime's trampolines which directly
read these registers.

* Fix pulley tests

* Free up `spilltmp1` register

Also unused in CLIF

cranelift/codegen/src/isa/pulley_shared/abi.rs

@@ -344,45 +344,24 @@ where
 
         let incoming_args_diff = frame_layout.tail_args_size - frame_layout.incoming_args_size;
         if incoming_args_diff > 0 {
+            // Pulley does not generate/probestack/stack checks/etc and doesn't
+            // expose the direct ability to modify fp/lr, so simulate a pop,
+            // perform the sp adjustment, then perform the same push that was
+            // done previously in the prologue.
+            //
+            // Note that for now this'll generate `push_frame pop_frame` pairs
+            // in the prologue which isn't great, and updating that is left for
+            // a future refactoring to only do a `push_frame` once (e.g. skip
+            // the one above if this block is going to be executed)
+            if setup_frame {
+                insts.push(RawInst::PopFrame.into());
+            }
             // Decrement SP by the amount of additional incoming argument space
             // we need
             insts.extend(Self::gen_sp_reg_adjust(-(incoming_args_diff as i32)));
 
             if setup_frame {
-                // Write the lr position on the stack again, as it hasn't
-                // changed since it was pushed in `gen_prologue_frame_setup`
-                insts.push(
-                    Inst::gen_store(
-                        Amode::SpOffset { offset: 8 },
-                        lr_reg(),
-                        I64,
-                        MemFlags::trusted(),
-                    )
-                    .into(),
-                );
-                insts.push(
-                    Inst::gen_load(
-                        writable_fp_reg(),
-                        Amode::SpOffset {
-                            offset: i32::try_from(incoming_args_diff).unwrap(),
-                        },
-                        I64,
-                        MemFlags::trusted(),
-                    )
-                    .into(),
-                );
-                insts.push(
-                    Inst::gen_store(
-                        Amode::SpOffset { offset: 0 },
-                        fp_reg(),
-                        I64,
-                        MemFlags::trusted(),
-                    )
-                    .into(),
-                );
-
-                // Finally, sync the frame pointer with SP.
-                insts.push(Self::I::gen_move(writable_fp_reg(), stack_reg(), I64));
+                insts.push(RawInst::PushFrame.into());
             }
         }
 

cranelift/codegen/src/isa/pulley_shared/inst.isle

@@ -380,12 +380,6 @@
 (decl sp_reg () XReg)
 (extern constructor sp_reg sp_reg)
 
-(decl fp_reg () XReg)
-(extern constructor fp_reg fp_reg)
-
-(decl lr_reg () XReg)
-(extern constructor lr_reg lr_reg)
-
 (decl pulley_get_special (XReg) XReg)
 (rule (pulley_get_special reg)
       (let ((dst WritableXReg (temp_writable_xreg))

cranelift/codegen/src/isa/pulley_shared/inst/regs.rs

@@ -89,12 +89,12 @@ define_registers! {
     x_reg(24) => x24, writable_x24;
     x_reg(25) => x25, writable_x25;
     x_reg(26) => x26, writable_x26;
+    x_reg(27) => x27, writable_x27;
+    x_reg(28) => x28, writable_x28;
+    x_reg(29) => x29, writable_x29;
 
-    x_reg(27) => stack_reg, writable_stack_reg;
-    x_reg(28) => lr_reg, writable_lr_reg;
-    x_reg(29) => fp_reg, writable_fp_reg;
-    x_reg(30) => spilltmp_reg, writable_spilltmp_reg;
-    x_reg(31) => spilltmp2_reg, writable_spilltmp2_reg;
+    x_reg(30) => stack_reg, writable_stack_reg;
+    x_reg(31) => spilltmp_reg, writable_spilltmp_reg;
 
     f_reg(0) => f0, writable_f0;
     f_reg(1) => f1, writable_f1;

cranelift/codegen/src/isa/pulley_shared/lower.isle

@@ -86,13 +86,11 @@
 
 ;;;; Rules for `get_frame_pointer` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(rule (lower (get_frame_pointer))
-      (pulley_get_special (fp_reg)))
+(rule (lower (get_frame_pointer)) (pulley_xmov_fp))
 
 ;;;; Rules for `get_return_address` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(rule (lower (get_return_address))
-      (pulley_get_special (lr_reg)))
+(rule (lower (get_return_address)) (pulley_xmov_lr))
 
 ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 

cranelift/codegen/src/isa/pulley_shared/lower/isle.rs

@@ -107,14 +107,6 @@ where
         XReg::new(regs::stack_reg()).unwrap()
     }
 
-    fn fp_reg(&mut self) -> XReg {
-        XReg::new(regs::fp_reg()).unwrap()
-    }
-
-    fn lr_reg(&mut self) -> XReg {
-        XReg::new(regs::lr_reg()).unwrap()
-    }
-
     fn cond_invert(&mut self, cond: &Cond) -> Cond {
         cond.invert()
     }

cranelift/filetests/filetests/isa/pulley32/call.clif

@@ -228,37 +228,37 @@ block0:
 ; VCode:
 ;   push_frame
 ;   stack_alloc32 112
-;   xstore64 sp+104, x18 // flags =  notrap aligned
-;   xstore64 sp+96, x19 // flags =  notrap aligned
+;   xstore64 sp+104, x17 // flags =  notrap aligned
+;   xstore64 sp+96, x18 // flags =  notrap aligned
 ;   xstore64 sp+88, x20 // flags =  notrap aligned
 ;   xstore64 sp+80, x21 // flags =  notrap aligned
-;   xstore64 sp+72, x23 // flags =  notrap aligned
-;   xstore64 sp+64, x24 // flags =  notrap aligned
-;   xstore64 sp+56, x25 // flags =  notrap aligned
+;   xstore64 sp+72, x22 // flags =  notrap aligned
+;   xstore64 sp+64, x23 // flags =  notrap aligned
+;   xstore64 sp+56, x29 // flags =  notrap aligned
 ; block0:
 ;   x0 = load_addr OutgoingArg(0)
 ;   call CallInfo { dest: TestCase(%g), uses: [CallArgPair { vreg: p0i, preg: p0i }], defs: [CallRetPair { vreg: Writable { reg: p0i }, preg: p0i }, CallRetPair { vreg: Writable { reg: p1i }, preg: p1i }, CallRetPair { vreg: Writable { reg: p2i }, preg: p2i }, CallRetPair { vreg: Writable { reg: p3i }, preg: p3i }, CallRetPair { vreg: Writable { reg: p4i }, preg: p4i }, CallRetPair { vreg: Writable { reg: p5i }, preg: p5i }, CallRetPair { vreg: Writable { reg: p6i }, preg: p6i }, CallRetPair { vreg: Writable { reg: p7i }, preg: p7i }, CallRetPair { vreg: Writable { reg: p8i }, preg: p8i }, CallRetPair { vreg: Writable { reg: p9i }, preg: p9i }, CallRetPair { vreg: Writable { reg: p10i }, preg: p10i }, CallRetPair { vreg: Writable { reg: p11i }, preg: p11i }, CallRetPair { vreg: Writable { reg: p12i }, preg: p12i }, CallRetPair { vreg: Writable { reg: p13i }, preg: p13i }, CallRetPair { vreg: Writable { reg: p14i }, preg: p14i }, CallRetPair { vreg: Writable { reg: p15i }, preg: p15i }], clobbers: PRegSet { bits: [0, 65279, 4294967295, 0] }, callee_conv: Fast, caller_conv: Fast, callee_pop_size: 0 }
-;   xmov x18, x13
-;   xmov x20, x11
-;   x24 = xload64 OutgoingArg(0) // flags = notrap aligned
+;   xmov x20, x13
+;   xmov x22, x11
+;   x29 = xload64 OutgoingArg(0) // flags = notrap aligned
 ;   x11 = xload64 OutgoingArg(8) // flags = notrap aligned
 ;   x13 = xload64 OutgoingArg(16) // flags = notrap aligned
-;   x19 = xload64 OutgoingArg(24) // flags = notrap aligned
-;   x21 = xload64 OutgoingArg(32) // flags = notrap aligned
-;   xadd64 x25, x0, x1
-;   xadd64 x23, x2, x3
+;   x21 = xload64 OutgoingArg(24) // flags = notrap aligned
+;   x23 = xload64 OutgoingArg(32) // flags = notrap aligned
+;   xadd64 x18, x0, x1
+;   xadd64 x17, x2, x3
 ;   xadd64 x5, x4, x5
 ;   xadd64 x6, x6, x7
 ;   xadd64 x7, x8, x9
-;   xmov x0, x20
+;   xmov x0, x22
 ;   xadd64 x4, x10, x0
-;   xmov x10, x18
+;   xmov x10, x20
 ;   xadd64 x8, x12, x10
 ;   xadd64 x14, x14, x15
-;   xadd64 x15, x24, x11
+;   xadd64 x15, x29, x11
 ;   xadd64 x13, x11, x13
-;   xadd64 x0, x19, x21
-;   xadd64 x1, x25, x23
+;   xadd64 x0, x21, x23
+;   xadd64 x1, x18, x17
 ;   xadd64 x2, x5, x6
 ;   xadd64 x3, x7, x4
 ;   xadd64 x14, x8, x14
@@ -270,50 +270,50 @@ block0:
 ;   xadd64 x14, x0, x14
 ;   xadd64 x13, x13, x13
 ;   xadd64 x0, x14, x13
-;   x18 = xload64 sp+104 // flags = notrap aligned
-;   x19 = xload64 sp+96 // flags = notrap aligned
+;   x17 = xload64 sp+104 // flags = notrap aligned
+;   x18 = xload64 sp+96 // flags = notrap aligned
 ;   x20 = xload64 sp+88 // flags = notrap aligned
 ;   x21 = xload64 sp+80 // flags = notrap aligned
-;   x23 = xload64 sp+72 // flags = notrap aligned
-;   x24 = xload64 sp+64 // flags = notrap aligned
-;   x25 = xload64 sp+56 // flags = notrap aligned
+;   x22 = xload64 sp+72 // flags = notrap aligned
+;   x23 = xload64 sp+64 // flags = notrap aligned
+;   x29 = xload64 sp+56 // flags = notrap aligned
 ;   stack_free32 112
 ;   pop_frame
 ;   ret
 ;
 ; Disassembled:
 ; push_frame
 ; stack_alloc32 112
-; xstore64le_offset32 sp, 104, x18
-; xstore64le_offset32 sp, 96, x19
+; xstore64le_offset32 sp, 104, x17
+; xstore64le_offset32 sp, 96, x18
 ; xstore64le_offset32 sp, 88, x20
 ; xstore64le_offset32 sp, 80, x21
-; xstore64le_offset32 sp, 72, x23
-; xstore64le_offset32 sp, 64, x24
-; xstore64le_offset32 sp, 56, x25
+; xstore64le_offset32 sp, 72, x22
+; xstore64le_offset32 sp, 64, x23
+; xstore64le_offset32 sp, 56, x29
 ; xmov x0, sp
 ; call 0x0    // target = 0x3a
-; xmov x18, x13
-; xmov x20, x11
-; xload64le_offset32 x24, sp, 0
+; xmov x20, x13
+; xmov x22, x11
+; xload64le_offset32 x29, sp, 0
 ; xload64le_offset32 x11, sp, 8
 ; xload64le_offset32 x13, sp, 16
-; xload64le_offset32 x19, sp, 24
-; xload64le_offset32 x21, sp, 32
-; xadd64 x25, x0, x1
-; xadd64 x23, x2, x3
+; xload64le_offset32 x21, sp, 24
+; xload64le_offset32 x23, sp, 32
+; xadd64 x18, x0, x1
+; xadd64 x17, x2, x3
 ; xadd64 x5, x4, x5
 ; xadd64 x6, x6, x7
 ; xadd64 x7, x8, x9
-; xmov x0, x20
+; xmov x0, x22
 ; xadd64 x4, x10, x0
-; xmov x10, x18
+; xmov x10, x20
 ; xadd64 x8, x12, x10
 ; xadd64 x14, x14, x15
-; xadd64 x15, x24, x11
+; xadd64 x15, x29, x11
 ; xadd64 x13, x11, x13
-; xadd64 x0, x19, x21
-; xadd64 x1, x25, x23
+; xadd64 x0, x21, x23
+; xadd64 x1, x18, x17
 ; xadd64 x2, x5, x6
 ; xadd64 x3, x7, x4
 ; xadd64 x14, x8, x14
@@ -325,13 +325,13 @@ block0:
 ; xadd64 x14, x0, x14
 ; xadd64 x13, x13, x13
 ; xadd64 x0, x14, x13
-; xload64le_offset32 x18, sp, 104
-; xload64le_offset32 x19, sp, 96
+; xload64le_offset32 x17, sp, 104
+; xload64le_offset32 x18, sp, 96
 ; xload64le_offset32 x20, sp, 88
 ; xload64le_offset32 x21, sp, 80
-; xload64le_offset32 x23, sp, 72
-; xload64le_offset32 x24, sp, 64
-; xload64le_offset32 x25, sp, 56
+; xload64le_offset32 x22, sp, 72
+; xload64le_offset32 x23, sp, 64
+; xload64le_offset32 x29, sp, 56
 ; stack_free32 112
 ; pop_frame
 ; ret

cranelift/filetests/filetests/isa/pulley32/special_regs.clif

@@ -11,7 +11,7 @@ block0:
 ; VCode:
 ;   push_frame
 ; block0:
-;   xmov x0, x27
+;   xmov x0, x30
 ;   pop_frame
 ;   ret
 ;
@@ -30,13 +30,13 @@ block0:
 ; VCode:
 ;   push_frame
 ; block0:
-;   xmov x0, x29
+;   xmov_fp x0
 ;   pop_frame
 ;   ret
 ;
 ; Disassembled:
 ; push_frame
-; xmov x0, fp
+; xmov_fp x0
 ; pop_frame
 ; ret
 
@@ -49,13 +49,13 @@ block0:
 ; VCode:
 ;   push_frame
 ; block0:
-;   xmov x0, x28
+;   xmov_lr x0
 ;   pop_frame
 ;   ret
 ;
 ; Disassembled:
 ; push_frame
-; xmov x0, lr
+; xmov_lr x0
 ; pop_frame
 ; ret