bonfire-basic-soc

Simple SOC which uses only internal FPGA ressources and can be synthesized and simulated easily

Name		Name	Last commit message	Last commit date
Latest commit History 35 Commits
cmods7		cmods7
compiled_code		compiled_code
memory		memory
sdram		sdram
tb		tb
ulx3s		ulx3s
vivado		vivado
.gitignore		.gitignore
Arty.xdc		Arty.xdc
LICENSE		LICENSE
MainMemory.vhd		MainMemory.vhd
README.md		README.md
blockram.gtkw		blockram.gtkw
bonfire-basic-soc.core		bonfire-basic-soc.core
bonfire-core-basic-soc.core		bonfire-core-basic-soc.core
bonfire_basic_soc.vhd		bonfire_basic_soc.vhd
bonfire_basic_soc_top.vhd		bonfire_basic_soc_top.vhd
bonfire_core_basic_soc.vhd		bonfire_core_basic_soc.vhd
bug_search.gtkw		bug_search.gtkw
cpu_dbus_connect.vhd		cpu_dbus_connect.vhd
csr.gtkw		csr.gtkw
dram_arbiter.vhd		dram_arbiter.vhd
gpio_pad.vhd		gpio_pad.vhd
pll.sbx		pll.sbx
soc_arty_top.vhd		soc_arty_top.vhd
soc_fireant_top.vhd		soc_fireant_top.vhd
test2023.gtkw		test2023.gtkw
wbs_memory_interface.vhd		wbs_memory_interface.vhd

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