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s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints
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This leverages commit ("s390: Simplify (dis)assembly of insn operands
with const bits") to relax the operand constraints of the immediate
operand that contains the constant Z- or T-bit of the following extended
mnemonics:
risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt

Previously those instructions were the only ones where the assembler
on s390 restricted the specification of the subject I3/I4 operand values
exactly according to their specification to an unsigned 6- or 5-bit
unsigned integer. For any other instructions the assembler allows to
specify any operand value allowed by the instruction format, regardless
of whether the instruction specification is more restrictive.

Allow to specify the subject I3/I4 operand as unsigned 8-bit integer
with the constant operand bits being ORed during assembly.
Relax the instructions subject significant operand bit masks to only
consider the Z/T-bit as significant, so that the instructions get
disassembled as their *z or *t flavor regardless of whether any reserved
bits are set in addition to the Z/T-bit.
Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set
the T-bit in operand I3, as they otherwise get disassembled as their
rnsbgt, rosbgt, and rxsbgt counterpart.

This aligns GNU Assembler to LLVM Assembler.

opcodes/
	* s390-opc.c (U6_18, U5_27, U6_26): Remove.
	(INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define
	as INSTR_RIE_RRUUU while retaining insn fmt mask.
	(MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only
	Z/T-bit of I3/I4 operand as significant.

gas/testsuite/
	* gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit.

Reported-by: Dominik Steenken <[email protected]>
Suggested-by: Ulrich Weigand <[email protected]>
Signed-off-by: Jens Remus <[email protected]>
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Jens Remus committed Sep 12, 2024
1 parent a3f1e7c commit b8b60e2
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Showing 3 changed files with 21 additions and 27 deletions.
12 changes: 6 additions & 6 deletions gas/testsuite/gas/s390/zarch-z10.d
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Original file line number Diff line number Diff line change
Expand Up @@ -359,20 +359,20 @@ Disassembly of section .text:
.*: c2 60 ff fe 79 60 [ ]*msgfi %r6,-100000
.*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\)
*([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 <foo\+0x\1>
.*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
.*: ec 67 d2 dc 00 54 [ ]*rnsbg %r6,%r7,210,220
.*: ec 67 6e dc e6 54 [ ]*rnsbg %r6,%r7,110,220,230
.*: ec 67 6e dc 00 54 [ ]*rnsbg %r6,%r7,110,220
.*: ec 67 92 dc e6 54 [ ]*rnsbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 54 [ ]*rnsbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 54 [ ]*rnsbgt %r6,%r7,18,28,38
.*: ec 67 92 1c 00 54 [ ]*rnsbgt %r6,%r7,18,28
.*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
.*: ec 67 d2 dc 00 57 [ ]*rxsbg %r6,%r7,210,220
.*: ec 67 6e dc e6 57 [ ]*rxsbg %r6,%r7,110,220,230
.*: ec 67 6e dc 00 57 [ ]*rxsbg %r6,%r7,110,220
.*: ec 67 92 dc e6 57 [ ]*rxsbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 57 [ ]*rxsbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 57 [ ]*rxsbgt %r6,%r7,18,28,38
.*: ec 67 92 1c 00 57 [ ]*rxsbgt %r6,%r7,18,28
.*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
.*: ec 67 d2 dc 00 56 [ ]*rosbg %r6,%r7,210,220
.*: ec 67 6e dc e6 56 [ ]*rosbg %r6,%r7,110,220,230
.*: ec 67 6e dc 00 56 [ ]*rosbg %r6,%r7,110,220
.*: ec 67 92 dc e6 56 [ ]*rosbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 56 [ ]*rosbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 56 [ ]*rosbgt %r6,%r7,18,28,38
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12 changes: 6 additions & 6 deletions gas/testsuite/gas/s390/zarch-z10.s
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Original file line number Diff line number Diff line change
Expand Up @@ -353,20 +353,20 @@ foo:
msgfi %r6,-100000
pfd 10,5555(%r6,%r7)
pfdrl 10,.
rnsbg %r6,%r7,210,220,230
rnsbg %r6,%r7,210,220
rnsbg %r6,%r7,110,220,230
rnsbg %r6,%r7,110,220
rnsbg %r6,%r7,146,220,230
rnsbg %r6,%r7,146,220
rnsbgt %r6,%r7,18,28,38
rnsbgt %r6,%r7,18,28
rxsbg %r6,%r7,210,220,230
rxsbg %r6,%r7,210,220
rxsbg %r6,%r7,110,220,230
rxsbg %r6,%r7,110,220
rxsbg %r6,%r7,146,220,230
rxsbg %r6,%r7,146,220
rxsbgt %r6,%r7,18,28,38
rxsbgt %r6,%r7,18,28
rosbg %r6,%r7,210,220,230
rosbg %r6,%r7,210,220
rosbg %r6,%r7,110,220,230
rosbg %r6,%r7,110,220
rosbg %r6,%r7,146,220,230
rosbg %r6,%r7,146,220
rosbgt %r6,%r7,18,28,38
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24 changes: 9 additions & 15 deletions opcodes/s390-opc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -216,15 +216,9 @@ const struct s390_operand s390_operands[] =
{ 4, 36, 0 },
#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */
{ 8, 8, 0 },
#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */
{ 6, 18, 0 },
#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */
#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */
{ 5, 27, 0 },
#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */
{ 6, 26, 0 },
#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */
#define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */
{ 8, 24, 0 },
#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */
{ 8, 28, 0 },
Expand Down Expand Up @@ -288,7 +282,7 @@ unused_s390_operands_static_asserts (void)
p - pc relative
r - general purpose register
re - gpr extended operand, a valid general purpose register pair
u - unsigned integer, 4, 6, 8, 16 or 32 bit
u - unsigned integer, 4, 8, 16 or 32 bit
m - mode field, 4 bit
0 - operand skipped.
The order of the letters reflects the layout of the format in
Expand Down Expand Up @@ -324,9 +318,9 @@ unused_s390_operands_static_asserts (void)
#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */
#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */
#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */
#define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */
#define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */
#define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
Expand Down Expand Up @@ -551,9 +545,9 @@ unused_s390_operands_static_asserts (void)
#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff }
#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff }
#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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