WIP: stm32 flash rework + ch32 flash rework and implementation#1642

Draft

perigoso wants to merge 130 commits intoblackmagic-debug:mainfrom perigoso:fix/stm32-flash-rework

+6,133-1,433

Commits on Oct 3, 2023

riscv_debug: Begun building a scan handler for RISC-V debug v0.13 devices

dragonmux
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riscv_debug: Created a stub for initialising a DMI

dragonmux
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riscv_debug: Implemented a way to read/write the DTM control/status register

dragonmux
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riscv_debug: Moved the JTAG-specific DTM handler into the JTAG DTM implementation file

dragonmux
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riscv_debug: Implemented support for reading and dispatching the DTM version

dragonmux
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riscv_debug: Implemented reference counting and stub structures for the DMs and Harts

dragonmux
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riscv_debug: Restructed riscv_dmi_init() and riscv_jtag_dtm_init() to prepare for scanning for DMs

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riscv_debug: Handle the idle cycles component of the DTMCS register

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riscv_debug: Implemented a way to read the DMI address space

dragonmux
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riscv_debug: Implemented logic for iterating and discovering DMs

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riscv_debug: Begun implementing the hart enumeration process

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riscv_debug: Implemented enumeration of the harts associated with a DM

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riscv_debug: Implemented support for grabbing the hart's address bus width and system bus version

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riscv_debug: Implemented halt and resume support in preparation for reading CSRs and memory from a hart

dragonmux
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riscv_debug: Implemented readout of CSRs and reading the 4 hart identification registers

dragonmux
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riscv_debug: Implemented readout of the ISA register to determine address width

dragonmux
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riscv_debug: Implemented the ability for riscv_reg_read() to do 128-, 64-, and 32-bit reads as required

dragonmux
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riscv_debug: Implemented support for discovering the target Hart's ISA and access width

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riscv_debug: Implemented writing to CSRs

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riscv_debug: Created probe stubs for probing RISC-V 32- and 64-bit targets

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riscv_debug: Set up the target designer code field

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riscv_debug: Documented the used CSR addresses

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riscv_debug: Implemented the ability to force a CSR access to a specific width

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riscv_debug: Implemented single-stepping support in riscv_halt_resume()

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riscv_debug: Added definitions for the abstract memory access command

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riscv_debug: Implemented arbitrary memory read

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riscv_debug: Fixed the target hart not being halted during probing

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riscv_debug: Added some DEBUG_TARGET information to the CSR functions and a failure warning to the CSR wait complete function

dragonmux
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riscv_debug: Implemented the target check_error hook

dragonmux
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riscv_debug: Made more of the DM and hart machinary available in the header

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riscv_debug: Moved the mem_read implementation into the bitness-specific implementations as the access width depends on the address width for memory

dragonmux
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riscv_debug: Forced the vendor ID to be read 32-bit per the privileged spec

dragonmux
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stm32f1: Implemented a probe routine for GD32VF1

dragonmux
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riscv32: Implemented probing for the GD32VF1

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riscv_debug: Handle the rv128 case by complaining to the user we don't support the hart and exiting fast from riscv_hart_init()

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riscv_debug: Begun implementing attach/detach

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riscv_debug: Populated target->cpuid and made use of it in gd32vf1_probe() for an even more positive part identification

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riscv_debug: Implemented building the target description XML

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riscv_debug: Implemented regs_read for both rv32 and rv64

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riscv_debug: Halt the hart we're looking at to on attach, and resume it on detach

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riscv32: Added some better documentation for what various things do

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riscv64: Added some better documentation for what various things do

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riscv_debug: Fixed a couple of mistakes in the comments for riscv_dmi_init()

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riscv_debug: Implemented the target halt_poll hook

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riscv_debug: Implemented discovery of the available "trigger" slots and what kinds of triggers they each support

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riscv_debug: Implemented support machinary for being able to set watch and breakpoints

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riscv_debug: Added documentation on where to find the debug specs used

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riscv_debug: Implemented a translator for a breakwatch size to match size

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riscv32: Implemented the target breakwatch_set hook

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riscv32: Implemented the target breakwatch_clear hook

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gdb_main: Added some comments to aid with understanding handle_z_packet()

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stm32f1: Modified the Flash routines to work with GD32VF103 parts too

dragonmux
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riscv_debug: Moved the part ID readout into its own function, fixing operation on rv64

dragonmux
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riscv_debug: Implemented target reset

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riscv_debug: Refactored out the DM state polling code into a new function

dragonmux
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riscv_debug: Implemented polling for reset succeeding and then acknowledgement of the reset

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riscv32: Improved the checks in riscv32_breakwatch_set() to avoid using unsuitable trigger slots

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riscv_debug: Cleaned up the nomenclature of riscv_halt_poll()'s halt causes enum

dragonmux
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riscv_debug: Implemented regs_write for both rv32 and rv64

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riscv32: Implemented mem_write and a data packing helper

dragonmux
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riscv_debug: Transform JTAG ID Code designer into JEP-106 internal format and store it as a DMI designer code

perigoso
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riscv_debug: Fixed the vendor ID decode in riscv_hart_read_ids() to adjust for BMD's representation of JEP-106 codes

dragonmux
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riscv_debug: Implemented poll timeouts for halt/resume

dragonmux
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riscv: check if hw reset worked, if not do a DM reset

mean
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riscv: make sure the hart is stopped when exiting reset

mean
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riscv: add single register access, add csr access with an offset, expose some CSRs register in the xml description

mean
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fixup! riscv32: Implemented probing for the GD32VF1

perigoso
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jtag_devs: Added the ESP32-C3's IDCode to the devices table

dragonmux
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riscv_debug: Too wide a CSR access triggers a not-supported error on ESP32-C3

dragonmux
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jep106: Added the manufacturer code for Espressif

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riscv_debug: Implemented DMI sticky error recovery

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jtag_devs: Added IR quirks for the ESP32-C3

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riscv_jtag_dtm: Fixed riscv_shift_dmi() not implementing handling for RV_DMI_TOO_SOON

dragonmux
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riscv_debug: Added in some additional target-level logging in the DMI read/write routines

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riscv_jtag_dtm: Adjusted riscv_jtag_dmi_write() with handling for RV_DMI_TOO_SOON

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esp32c3: Began implementing support and memory maps for the ESP32-C3

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esp32c3: Began the process of implementing support for the off-chip Flash, starting with the mappings

dragonmux
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riscv32: Refactored the memory access routines to allow a target to specify use of system bus instead of abstract command for memory access

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riscv32: Moved the length check and target-level debugging for memory access into the overarching routines

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riscv_debug: Implemented support for detecting and switching over to the system bus interface for memory access

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riscv_debug: Naming cleanup of the constants involved in abstract command memory access

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riscv32: Implemented memory read via system bus

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riscv32: Fixed riscv32_sysbus_mem_read() not checking the system bus status after completion

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riscv32: Implemented memory write via sytem bus

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riscv_debug: Grabbed the supported system bus access widths in riscv_hart_memory_access_type()

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riscv32: Refactored out the native-width system bus access logic into a new function

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riscv32: Implemented support for non-native-width system bus memory reads

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riscv32: Added in a busy check to the native memory read loop to keep the target's system bus controller happy

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riscv_debug: Added some insurance that the system bus is in a good state before use

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esp32c3: Implemented support for performing SPI reads and reading out the SFDP data of the target

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esp32c3: Improved the fallback path in esp32c3_add_flash() when the SFDP readout fails

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riscv32: Added a loop to riscv32_sysbus_mem_write() to make sure each write completes before issuing the next

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esp32c3: Implemented handling for chunking reads to handle the fact the buffer's not otherwise big enough to handle all possible reads

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esp32c3: Implemented handling for disabling and restoring the WDTs so they stop destroying the debug environment

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riscv32: Refactored out the native-width system bus write logic into a new function

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riscv32: Implemented support for non-native-width system bus memory writes

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esp32c3: Implemented SPI write support and mass erase

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esp32c3: Implemented a type for holding SPI Flash specific information

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esp32c3: Implemented Flash erase

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esp32c3: Implemented Flash write

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esp32c3: Added handling for correctly entering Flash mode

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esp32c3: Implemented i-cache invalidation and reload for post-completion of Flash operations

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esp32c3: Improved the setup for esp32c3_spu_run_command()

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esp32c3: Refactored out the innards of esp32c3_spi_run_command() from esp32c3_spi_write()

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esp32c3: Improved our handling of chip select hold in esp32c3_spi_write()

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esp32c3: Cleaned up the handling of the SPI1 misc register in esp32c3_spi_read()

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esp32c3: Cleaned up and improved the data handling in esp32c3_spi_read() and esp32c3_spi_write()

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esp32c3: Hacky patch to make Flash write almost work correctly at the loss of a huge amount of speed (25% the speed)

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esp32c3: Switched errors over to using DEBUG_ERROR instead of abusing DEBUG_WARN

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target/esp32c3: fix sfdp function signature

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Commits on Oct 5, 2023

hosted: barebones wch-link implementation

perigoso
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buffer_utils: Implemented a big endian 32-bit write

perigoso
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hosted/wchlink: implement DMI transfer

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riscv_debug: expose DMI operation and status defines

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jep106: add BMD internal flag

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jep106: add internal WCH non-jep106 code

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riscv_jtag_dtm: move RV_DMI_TOO_SOON handling one level up

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hosted/wchlink: implement RISC-V DTM handler

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command: add rvswd scan routine command

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hosted/wchlink: implement RVSWD scan

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riscv_debug: handle CH32V3x quirk

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riscv32: add ch32v3 target probe

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!fixme! mass erase rework, drop after merge and rebase

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esp32c3: refactor with new mass erase target API

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ch32vx: implement electronic signature (ESIG) register handling

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target/ch32f1: replace macros with functions

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target/ch32f1: longer variable naming

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target/ch32f1: remove debug verify code

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target/ch32f1: const correctness

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!fixme! stm32 flash

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