Auto merge of rust-lang#125732 - matthiaskrgr:rollup-bozbtk3, r=matth…

…iaskrgr

Rollup of 7 pull requests

Successful merges:

 - rust-lang#124655 (Add `-Zfixed-x18`)
 - rust-lang#125693 (Format all source files in `tests/coverage/`)
 - rust-lang#125700 (coverage: Avoid overflow when the MC/DC condition limit is exceeded)
 - rust-lang#125705 (Reintroduce name resolution check for trying to access locals from an inline const)
 - rust-lang#125708 (tier 3 target policy: clarify the point about producing assembly)
 - rust-lang#125715 (remove unneeded extern crate in rmake test)
 - rust-lang#125719 (Extract coverage-specific code out of `compiletest::runtest`)

r? `@ghost`
`@rustbot` modify labels: rollup

compiler/rustc_codegen_llvm/messages.ftl

@@ -18,6 +18,8 @@ codegen_llvm_error_creating_import_library =
 codegen_llvm_error_writing_def_file =
     Error writing .DEF file: {$error}
 
+codegen_llvm_fixed_x18_invalid_arch = the `-Zfixed-x18` flag is not supported on the `{$arch}` architecture
+
 codegen_llvm_from_llvm_diag = {$message}
 
 codegen_llvm_from_llvm_optimization_diag = {$filename}:{$line}:{$column} {$pass_name} ({$kind}): {$message}

compiler/rustc_codegen_llvm/src/errors.rs

@@ -254,3 +254,9 @@ pub struct MismatchedDataLayout<'a> {
 pub(crate) struct InvalidTargetFeaturePrefix<'a> {
     pub feature: &'a str,
 }
+
+#[derive(Diagnostic)]
+#[diag(codegen_llvm_fixed_x18_invalid_arch)]
+pub(crate) struct FixedX18InvalidArch<'a> {
+    pub arch: &'a str,
+}

compiler/rustc_codegen_llvm/src/llvm_util.rs

@@ -1,6 +1,6 @@
 use crate::back::write::create_informational_target_machine;
 use crate::errors::{
-    InvalidTargetFeaturePrefix, PossibleFeature, TargetFeatureDisableOrEnable,
+    FixedX18InvalidArch, InvalidTargetFeaturePrefix, PossibleFeature, TargetFeatureDisableOrEnable,
     UnknownCTargetFeature, UnknownCTargetFeaturePrefix, UnstableCTargetFeature,
 };
 use crate::llvm;
@@ -615,6 +615,15 @@ pub(crate) fn global_llvm_features(sess: &Session, diagnostics: bool) -> Vec<Str
         .flatten();
     features.extend(feats);
 
+    // -Zfixed-x18
+    if sess.opts.unstable_opts.fixed_x18 {
+        if sess.target.arch != "aarch64" {
+            sess.dcx().emit_fatal(FixedX18InvalidArch { arch: &sess.target.arch });
+        } else {
+            features.push("+reserve-x18".into());
+        }
+    }
+
     if diagnostics && let Some(f) = check_tied_features(sess, &featsmap) {
         sess.dcx().emit_err(TargetFeatureDisableOrEnable {
             features: f,

compiler/rustc_interface/src/tests.rs

@@ -773,6 +773,7 @@ fn test_unstable_options_tracking_hash() {
     tracked!(emit_thin_lto, false);
     tracked!(export_executable_symbols, true);
     tracked!(fewer_names, Some(true));
+    tracked!(fixed_x18, true);
     tracked!(flatten_format_args, false);
     tracked!(force_unstable_if_unmarked, true);
     tracked!(fuel, Some(("abc".to_string(), 99)));

compiler/rustc_mir_build/src/build/coverageinfo/mcdc.rs

@@ -217,12 +217,13 @@ impl MCDCInfoBuilder {
                 }
                 _ => {
                     // Do not generate mcdc mappings and statements for decisions with too many conditions.
-                    let rebase_idx = self.branch_spans.len() - decision.conditions_num + 1;
+                    // Therefore, first erase the condition info of the (N-1) previous branch spans.
+                    let rebase_idx = self.branch_spans.len() - (decision.conditions_num - 1);
                     for branch in &mut self.branch_spans[rebase_idx..] {
                         branch.condition_info = None;
                     }
 
-                    // ConditionInfo of this branch shall also be reset.
+                    // Then, erase this last branch span's info too, for a total of N.
                     condition_info = None;
 
                     tcx.dcx().emit_warn(MCDCExceedsConditionNumLimit {

compiler/rustc_resolve/src/late.rs

@@ -4505,6 +4505,11 @@ impl<'a: 'ast, 'b, 'ast, 'tcx> LateResolutionVisitor<'a, 'b, 'ast, 'tcx> {
                 self.visit_expr(elem);
                 self.resolve_anon_const(ct, AnonConstKind::ConstArg(IsRepeatExpr::Yes));
             }
+            ExprKind::ConstBlock(ref expr) => {
+                self.resolve_anon_const_manual(false, AnonConstKind::InlineConst, |this| {
+                    this.visit_expr(expr)
+                });
+            }
             ExprKind::Index(ref elem, ref idx, _) => {
                 self.resolve_expr(elem, Some(expr));
                 self.visit_expr(idx);

compiler/rustc_session/src/options.rs

@@ -1678,6 +1678,8 @@ options! {
     fewer_names: Option<bool> = (None, parse_opt_bool, [TRACKED],
         "reduce memory use by retaining fewer names within compilation artifacts (LLVM-IR) \
         (default: no)"),
+    fixed_x18: bool = (false, parse_bool, [TRACKED],
+        "make the x18 register reserved on AArch64 (default: no)"),
     flatten_format_args: bool = (true, parse_bool, [TRACKED],
         "flatten nested format_args!() and literals into a simplified format_args!() call \
         (default: yes)"),

src/doc/rustc/src/target-tier-policy.md

@@ -247,7 +247,8 @@ approved by the appropriate team for that shared code before acceptance.
     target may not have; use conditional compilation or runtime detection, as
     appropriate, to let each target run code supported by that target.
 - Tier 3 targets must be able to produce assembly using at least one of
-  rustc's supported backends from any host target.
+  rustc's supported backends from any host target. (Having support in a fork
+  of the backend is not sufficient, it must be upstream.)
 
 If a tier 3 target stops meeting these requirements, or the target maintainers
 no longer have interest or time, or the target shows no signs of activity and

src/doc/unstable-book/src/compiler-flags/fixed-x18.md

@@ -0,0 +1,32 @@
+# `fixed-x18`
+
+This option prevents the compiler from using the x18 register. It is only
+supported on aarch64.
+
+From the [ABI spec][arm-abi]:
+
+> X18 is the platform register and is reserved for the use of platform ABIs.
+> This is an additional temporary register on platforms that don't assign a
+> special meaning to it.
+
+This flag only has an effect when the x18 register would otherwise be considered
+a temporary register. When the flag is applied, x18 is always a reserved
+register.
+
+This flag is intended for use with the shadow call stack sanitizer. Generally,
+when that sanitizer is enabled, the x18 register is used to store a pointer to
+the shadow stack. Enabling this flag prevents the compiler from overwriting the
+shadow stack pointer with temporary data, which is necessary for the sanitizer
+to work correctly.
+
+Currently, the `-Zsanitizer=shadow-call-stack` flag is only supported on
+platforms that always treat x18 as a reserved register, and the `-Zfixed-x18`
+flag is not required to use the sanitizer on such platforms. However, the
+sanitizer may be supported on targets where this is not the case in the future.
+
+It is undefined behavior for `-Zsanitizer=shadow-call-stack` code to call into
+code where x18 is a temporary register. On the other hand, when you are *not*
+using the shadow call stack sanitizer, compilation units compiled with and
+without the `-Zfixed-x18` flag are compatible with each other.
+
+[arm-abi]: https://developer.arm.com/documentation/den0024/a/The-ABI-for-ARM-64-bit-Architecture/Register-use-in-the-AArch64-Procedure-Call-Standard/Parameters-in-general-purpose-registers